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[Hexagon] Renaming old multiclass for removal. Adding post-increment store classes and instruction defs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224949 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Colin LeMahieu
parent
a318a2faaf
commit
d25cfdb649
@ -712,7 +712,7 @@ SDNode *HexagonDAGToDAGISel::SelectIndexedStore(StoreSDNode *ST, SDLoc dl) {
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if (StoredVT == MVT::i64) Opcode = Hexagon::POST_STdri;
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else if (StoredVT == MVT::i32) Opcode = Hexagon::POST_STwri;
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else if (StoredVT == MVT::i16) Opcode = Hexagon::POST_SThri;
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else if (StoredVT == MVT::i8) Opcode = Hexagon::POST_STbri;
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else if (StoredVT == MVT::i8) Opcode = Hexagon::S2_storerb_pi;
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else llvm_unreachable("unknown memory type");
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// Build post increment store.
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@ -1432,8 +1432,8 @@ isConditionalStore (const MachineInstr* MI) const {
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case Hexagon::STrib_indexed_shl_cNotPt_V4 :
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case Hexagon::STrib_cPt :
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case Hexagon::STrib_cNotPt :
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case Hexagon::POST_STbri_cPt :
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case Hexagon::POST_STbri_cNotPt :
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case Hexagon::S2_pstorerbt_pi:
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case Hexagon::S2_pstorerbf_pi:
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case Hexagon::STrid_indexed_cPt :
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case Hexagon::STrid_indexed_cNotPt :
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case Hexagon::STrid_indexed_shl_cPt_V4 :
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@ -2656,6 +2656,102 @@ def: Pat<(i64 (sub (i64 DoubleRegs:$src1),
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//===----------------------------------------------------------------------===//
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///
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// Store doubleword.
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//===----------------------------------------------------------------------===//
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// Template class for non-predicated post increment stores with immediate offset
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//===----------------------------------------------------------------------===//
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let isPredicable = 1, hasSideEffects = 0, addrMode = PostInc in
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class T_store_pi <string mnemonic, RegisterClass RC, Operand ImmOp,
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bits<4> MajOp, bit isHalf >
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: STInst <(outs IntRegs:$_dst_),
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(ins IntRegs:$src1, ImmOp:$offset, RC:$src2),
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mnemonic#"($src1++#$offset) = $src2"#!if(isHalf, ".h", ""),
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[], "$src1 = $_dst_" >,
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AddrModeRel {
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bits<5> src1;
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bits<5> src2;
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bits<7> offset;
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bits<4> offsetBits;
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string ImmOpStr = !cast<string>(ImmOp);
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let offsetBits = !if (!eq(ImmOpStr, "s4_3Imm"), offset{6-3},
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!if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
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!if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
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/* s4_0Imm */ offset{3-0})));
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let isNVStorable = !if (!eq(ImmOpStr, "s4_3Imm"), 0, 1);
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let IClass = 0b1010;
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let Inst{27-25} = 0b101;
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let Inst{24-21} = MajOp;
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let Inst{20-16} = src1;
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let Inst{13} = 0b0;
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let Inst{12-8} = src2;
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let Inst{7} = 0b0;
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let Inst{6-3} = offsetBits;
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let Inst{1} = 0b0;
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}
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//===----------------------------------------------------------------------===//
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// Template class for predicated post increment stores with immediate offset
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//===----------------------------------------------------------------------===//
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let isPredicated = 1, hasSideEffects = 0, addrMode = PostInc in
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class T_pstore_pi <string mnemonic, RegisterClass RC, Operand ImmOp,
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bits<4> MajOp, bit isHalf, bit isPredNot, bit isPredNew >
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: STInst <(outs IntRegs:$_dst_),
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(ins PredRegs:$src1, IntRegs:$src2, ImmOp:$offset, RC:$src3),
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!if(isPredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
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") ")#mnemonic#"($src2++#$offset) = $src3"#!if(isHalf, ".h", ""),
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[], "$src2 = $_dst_" >,
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AddrModeRel {
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bits<2> src1;
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bits<5> src2;
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bits<7> offset;
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bits<5> src3;
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bits<4> offsetBits;
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string ImmOpStr = !cast<string>(ImmOp);
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let offsetBits = !if (!eq(ImmOpStr, "s4_3Imm"), offset{6-3},
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!if (!eq(ImmOpStr, "s4_2Imm"), offset{5-2},
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!if (!eq(ImmOpStr, "s4_1Imm"), offset{4-1},
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/* s4_0Imm */ offset{3-0})));
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let isNVStorable = !if (!eq(ImmOpStr, "s4_3Imm"), 0, 1);
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let isPredicatedNew = isPredNew;
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let isPredicatedFalse = isPredNot;
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let IClass = 0b1010;
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let Inst{27-25} = 0b101;
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let Inst{24-21} = MajOp;
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let Inst{20-16} = src2;
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let Inst{13} = 0b1;
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let Inst{12-8} = src3;
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let Inst{7} = isPredNew;
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let Inst{6-3} = offsetBits;
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let Inst{2} = isPredNot;
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let Inst{1-0} = src1;
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}
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multiclass ST_PostInc<string mnemonic, string BaseOp, RegisterClass RC,
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Operand ImmOp, bits<4> MajOp, bit isHalf = 0 > {
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let BaseOpcode = "POST_"#BaseOp in {
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def S2_#NAME#_pi : T_store_pi <mnemonic, RC, ImmOp, MajOp, isHalf>;
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// Predicated
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def S2_p#NAME#t_pi : T_pstore_pi <mnemonic, RC, ImmOp, MajOp, isHalf, 0, 0>;
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def S2_p#NAME#f_pi : T_pstore_pi <mnemonic, RC, ImmOp, MajOp, isHalf, 1, 0>;
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// Predicated new
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def S2_p#NAME#tnew_pi : T_pstore_pi <mnemonic, RC, ImmOp, MajOp,
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isHalf, 0, 1>;
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def S2_p#NAME#fnew_pi : T_pstore_pi <mnemonic, RC, ImmOp, MajOp,
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isHalf, 1, 1>;
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}
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}
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let accessSize = ByteAccess, isCodeGenOnly = 0 in
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defm storerb: ST_PostInc <"memb", "STrib", IntRegs, s4_0Imm, 0b1000>;
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//===----------------------------------------------------------------------===//
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// Post increment store
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@ -2683,7 +2779,7 @@ multiclass ST_PostInc_Pred<string mnemonic, RegisterClass RC,
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}
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let hasCtrlDep = 1, isNVStorable = 1, hasSideEffects = 0 in
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multiclass ST_PostInc<string mnemonic, string BaseOp, RegisterClass RC,
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multiclass ST_PostInc2<string mnemonic, string BaseOp, RegisterClass RC,
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Operand ImmOp> {
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let hasCtrlDep = 1, BaseOpcode = "POST_"#BaseOp in {
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@ -2701,16 +2797,15 @@ multiclass ST_PostInc<string mnemonic, string BaseOp, RegisterClass RC,
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}
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}
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defm POST_STbri: ST_PostInc <"memb", "STrib", IntRegs, s4_0Imm>, AddrModeRel;
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defm POST_SThri: ST_PostInc <"memh", "STrih", IntRegs, s4_1Imm>, AddrModeRel;
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defm POST_STwri: ST_PostInc <"memw", "STriw", IntRegs, s4_2Imm>, AddrModeRel;
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defm POST_SThri: ST_PostInc2 <"memh", "STrih", IntRegs, s4_1Imm>, AddrModeRel;
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defm POST_STwri: ST_PostInc2 <"memw", "STriw", IntRegs, s4_2Imm>, AddrModeRel;
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let isNVStorable = 0 in
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defm POST_STdri: ST_PostInc <"memd", "STrid", DoubleRegs, s4_3Imm>, AddrModeRel;
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defm POST_STdri: ST_PostInc2 <"memd", "STrid", DoubleRegs, s4_3Imm>, AddrModeRel;
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def : Pat<(post_truncsti8 (i32 IntRegs:$src1), IntRegs:$src2,
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s4_3ImmPred:$offset),
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(POST_STbri IntRegs:$src2, s4_0ImmPred:$offset, IntRegs:$src1)>;
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(S2_storerb_pi IntRegs:$src2, s4_0ImmPred:$offset, IntRegs:$src1)>;
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def : Pat<(post_truncsti16 (i32 IntRegs:$src1), IntRegs:$src2,
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s4_3ImmPred:$offset),
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14
test/MC/Disassembler/Hexagon/st.txt
Normal file
14
test/MC/Disassembler/Hexagon/st.txt
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@ -0,0 +1,14 @@
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# RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s
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0x28 0xd5 0x11 0xab
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# CHECK: memb(r17++#5) = r21
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0x2b 0xf5 0x11 0xab
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# CHECK: if (p3) memb(r17++#5) = r21
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0x2f 0xf5 0x11 0xab
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# CHECK: if (!p3) memb(r17++#5) = r21
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0x03 0x40 0x45 0x85 0xab 0xf5 0x11 0xab
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# CHECK: p3 = r5
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# CHECK-NEXT: if (p3.new) memb(r17++#5) = r21
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0x03 0x40 0x45 0x85 0xaf 0xf5 0x11 0xab
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# CHECK: p3 = r5
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# CHECK-NEXT: if (!p3.new) memb(r17++#5) = r21
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