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[mips] Implement the 'dins' aliases.
Traditionally GAS has provided automatic selection between dins, dinsm and dinsu. Binutils also disassembles all instructions in that family as 'dins' rather than the actual instruction. Reviewers: slthakur Differential Revision: https://reviews.llvm.org/D34877 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@313267 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Simon Dardis
parent
bc0f9d9517
commit
d2c2deaecc
@ -463,6 +463,8 @@ public:
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Match_RequiresSameSrcAndDst,
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Match_NoFCCRegisterForCurrentISA,
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Match_NonZeroOperandForSync,
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Match_RequiresPosSizeRange0_32,
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Match_RequiresPosSizeRange33_64,
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#define GET_OPERAND_DIAGNOSTIC_TYPES
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#include "MipsGenAsmMatcher.inc"
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#undef GET_OPERAND_DIAGNOSTIC_TYPES
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@ -4977,6 +4979,28 @@ unsigned MipsAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
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if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg())
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return Match_RequiresDifferentOperands;
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return Match_Success;
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case Mips::DINS:
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case Mips::DINS_MM64R6: {
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assert(Inst.getOperand(2).isImm() && Inst.getOperand(3).isImm() &&
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"Operands must be immediates for dins!");
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const signed Pos = Inst.getOperand(2).getImm();
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const signed Size = Inst.getOperand(3).getImm();
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if ((0 > (Pos + Size)) || ((Pos + Size) > 32))
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return Match_RequiresPosSizeRange0_32;
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return Match_Success;
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}
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case Mips::DINSM:
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case Mips::DINSM_MM64R6:
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case Mips::DINSU:
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case Mips::DINSU_MM64R6: {
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assert(Inst.getOperand(2).isImm() && Inst.getOperand(3).isImm() &&
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"Operands must be immediates for dinsm/dinsu!");
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const signed Pos = Inst.getOperand(2).getImm();
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const signed Size = Inst.getOperand(3).getImm();
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if ((32 >= (Pos + Size)) || ((Pos + Size) > 64))
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return Match_RequiresPosSizeRange33_64;
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return Match_Success;
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}
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}
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uint64_t TSFlags = getInstDesc(Inst.getOpcode()).TSFlags;
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@ -5169,6 +5193,18 @@ bool MipsAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
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case Match_MemSImm16:
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return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
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"expected memory with 16-bit signed offset");
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case Match_RequiresPosSizeRange0_32: {
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SMLoc ErrorStart = Operands[3]->getStartLoc();
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SMLoc ErrorEnd = Operands[4]->getEndLoc();
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return Error(ErrorStart, "size plus position are not in the range 0 .. 32",
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SMRange(ErrorStart, ErrorEnd));
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}
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case Match_RequiresPosSizeRange33_64: {
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SMLoc ErrorStart = Operands[3]->getStartLoc();
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SMLoc ErrorEnd = Operands[4]->getEndLoc();
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return Error(ErrorStart, "size plus position are not in the range 33 .. 64",
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SMRange(ErrorStart, ErrorEnd));
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}
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}
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llvm_unreachable("Implement any new match types added!");
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@ -519,6 +519,10 @@ static DecodeStatus
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DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address,
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const void *Decoder);
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template <typename InsnType>
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static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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@ -1051,6 +1055,60 @@ static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn,
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return MCDisassembler::Success;
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}
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// Override the generated disassembler to produce DINS all the time. This is
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// for feature / behaviour parity with binutils.
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template <typename InsnType>
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static DecodeStatus DecodeDINS(MCInst &MI, InsnType Insn, uint64_t Address,
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const void *Decoder) {
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unsigned Msbd = fieldFromInstruction(Insn, 11, 5);
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unsigned Lsb = fieldFromInstruction(Insn, 6, 5);
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unsigned Size = 0;
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unsigned Pos = 0;
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bool IsMicroMips = false;
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switch (MI.getOpcode()) {
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case Mips::DINS_MM64R6:
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IsMicroMips = true;
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LLVM_FALLTHROUGH;
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case Mips::DINS:
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Pos = Lsb;
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Size = Msbd + 1 - Pos;
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break;
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case Mips::DINSM_MM64R6:
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IsMicroMips = true;
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LLVM_FALLTHROUGH;
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case Mips::DINSM:
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Pos = Lsb;
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Size = Msbd + 33 - Pos;
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break;
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case Mips::DINSU_MM64R6:
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IsMicroMips = true;
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LLVM_FALLTHROUGH;
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case Mips::DINSU:
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Pos = Lsb + 32;
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// mbsd = pos + size - 33
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// mbsd - pos + 33 = size
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Size = Msbd + 33 - Pos;
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break;
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default:
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llvm_unreachable("Unknown DINS instruction!");
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}
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// Although the format of the instruction is similar, rs and rt are swapped
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// for microMIPS64R6.
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InsnType Rs = fieldFromInstruction(Insn, 21, 5);
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InsnType Rt = fieldFromInstruction(Insn, 16, 5);
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if (IsMicroMips)
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std::swap(Rs, Rt);
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MI.setOpcode(IsMicroMips ? Mips::DINS_MM64R6 : Mips::DINS);
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MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rt)));
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MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, Rs)));
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MI.addOperand(MCOperand::createImm(Pos));
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MI.addOperand(MCOperand::createImm(Size));
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return MCDisassembler::Success;
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}
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/// Read two bytes from the ArrayRef and return 16 bit halfword sorted
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/// according to the given endianness.
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static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address,
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@ -2260,15 +2318,10 @@ static DecodeStatus DecodeInsSize(MCInst &Inst,
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uint64_t Address,
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const void *Decoder) {
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// First we need to grab the pos(lsb) from MCInst.
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// This function only handles the 32 bit variants of ins, as dins
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// variants are handled differently.
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int Pos = Inst.getOperand(2).getImm();
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if (Inst.getOpcode() == Mips::DINSU)
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Pos += 32;
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int Size;
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if (Inst.getOpcode() == Mips::DINSM ||
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Inst.getOpcode() == Mips::DINSU)
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Size = (int) Insn - Pos + 33;
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else
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Size = (int) Insn - Pos + 1;
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int Size = (int) Insn - Pos + 1;
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Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size)));
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return MCDisassembler::Success;
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}
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@ -168,8 +168,9 @@ class DINSU_MM64R6_DESC : InsBase<"dinsu", GPR64Opnd, uimm5_plus32,
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immZExt5Plus1, MipsIns>;
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class DINSM_MM64R6_DESC : InsBase<"dinsm", GPR64Opnd, uimm5, uimm_range_2_64,
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immZExt5, immZExtRange2To64, MipsIns>;
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class DINS_MM64R6_DESC : InsBase<"dins", GPR64Opnd, uimm5, uimm5_inssize_plus1,
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immZExt5, immZExt5Plus1, MipsIns>;
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class DINS_MM64R6_DESC : InsBase<"dins", GPR64Opnd, uimm5_report_uimm6,
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uimm5_inssize_plus1, immZExt5, immZExt5Plus1,
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MipsIns>;
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class DMTC0_MM64R6_DESC : MTC0_MMR6_DESC_BASE<"dmtc0", COP0Opnd, GPR64Opnd,
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II_DMTC0>;
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class DMTC1_MM64R6_DESC : MTC1_MMR6_DESC_BASE<"dmtc1", FGR64Opnd, GPR64Opnd,
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@ -382,12 +383,14 @@ let DecoderNamespace = "MicroMipsR6" in {
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ISA_MICROMIPS64R6;
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def DMODU_MM64R6 : R6MMR6Rel, DMODU_MM64R6_DESC, DMODU_MM64R6_ENC,
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ISA_MICROMIPS64R6;
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def DINSU_MM64R6: R6MMR6Rel, DINSU_MM64R6_DESC, DINSU_MM64R6_ENC,
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ISA_MICROMIPS64R6;
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def DINSM_MM64R6: R6MMR6Rel, DINSM_MM64R6_DESC, DINSM_MM64R6_ENC,
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ISA_MICROMIPS64R6;
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def DINS_MM64R6: R6MMR6Rel, DINS_MM64R6_DESC, DINS_MM64R6_ENC,
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ISA_MICROMIPS64R6;
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let DecoderMethod = "DecodeDINS" in {
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def DINSU_MM64R6: R6MMR6Rel, DINSU_MM64R6_DESC, DINSU_MM64R6_ENC,
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ISA_MICROMIPS64R6;
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def DINSM_MM64R6: R6MMR6Rel, DINSM_MM64R6_DESC, DINSM_MM64R6_ENC,
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ISA_MICROMIPS64R6;
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def DINS_MM64R6: R6MMR6Rel, DINS_MM64R6_DESC, DINS_MM64R6_ENC,
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ISA_MICROMIPS64R6;
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}
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def DMTC0_MM64R6 : StdMMR6Rel, DMTC0_MM64R6_ENC, DMTC0_MM64R6_DESC,
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ISA_MICROMIPS64R6;
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def DMTC1_MM64R6 : StdMMR6Rel, DMTC1_MM64R6_DESC, DMTC1_MM64R6_ENC,
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@ -562,3 +565,10 @@ def : MipsInstAlias<"dsrl $rd, $rt",
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def : MipsInstAlias<"dsll $rd, $rt",
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(DSLLV_MM64R6 GPR64Opnd:$rd, GPR64Opnd:$rd,
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GPR32Opnd:$rt), 0>, ISA_MICROMIPS64R6;
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def : MipsInstAlias<"dins $rt, $rs, $pos, $size",
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(DINSM_MM64R6 GPR64Opnd:$rt, GPR64Opnd:$rs, uimm5:$pos,
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uimm_range_2_64:$size), 0>, ISA_MICROMIPS64R6;
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def : MipsInstAlias<"dins $rt, $rs, $pos, $size",
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(DINSU_MM64R6 GPR64Opnd:$rt, GPR64Opnd:$rs,
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uimm5_plus32:$pos, uimm5_plus1:$size), 0>,
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ISA_MICROMIPS64R6;
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@ -327,14 +327,23 @@ let AdditionalPredicates = [NotInMicroMips] in {
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def DEXTU : ExtBase<"dextu", GPR64Opnd, uimm5_plus32, uimm5_plus1,
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immZExt5Plus32, immZExt5Plus1, MipsExt>, EXT_FM<2>,
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ISA_MIPS64R2;
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def DINS : InsBase<"dins", GPR64Opnd, uimm6, uimm5_inssize_plus1, immZExt5,
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immZExt5Plus1, MipsIns>, EXT_FM<7>, ISA_MIPS64R2;
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def DINSU : InsBase<"dinsu", GPR64Opnd, uimm5_plus32, uimm5_inssize_plus1,
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immZExt5Plus32, immZExt5Plus1, MipsIns>,
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EXT_FM<6>, ISA_MIPS64R2;
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def DINSM : InsBase<"dinsm", GPR64Opnd, uimm5, uimm_range_2_64,
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immZExt5, immZExtRange2To64, MipsIns>,
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EXT_FM<5>, ISA_MIPS64R2;
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// The 'pos + size' constraints for code generation are enforced by the
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// code that lowers into MipsISD::Ins.
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// For assembly parsing, we alias dinsu and dinsm to dins, and match by
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// operand were possible then check the 'pos + size' in MipsAsmParser.
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// We override the generated decoder to enforce that dins always comes out
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// for dinsm and dinsu like binutils.
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let DecoderMethod = "DecodeDINS" in {
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def DINS : InsBase<"dins", GPR64Opnd, uimm6, uimm5_inssize_plus1,
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immZExt5, immZExt5Plus1, MipsIns>, EXT_FM<7>,
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ISA_MIPS64R2;
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def DINSU : InsBase<"dinsu", GPR64Opnd, uimm5_plus32, uimm5_inssize_plus1,
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immZExt5Plus32, immZExt5Plus1, MipsIns>,
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EXT_FM<6>, ISA_MIPS64R2;
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def DINSM : InsBase<"dinsm", GPR64Opnd, uimm5, uimm_range_2_64,
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immZExt5, immZExtRange2To64, MipsIns>,
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EXT_FM<5>, ISA_MIPS64R2;
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}
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}
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let isCodeGenOnly = 1, AdditionalPredicates = [NotInMicroMips] in {
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@ -825,6 +834,12 @@ let AdditionalPredicates = [NotInMicroMips] in {
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def : MipsInstAlias<"dsll $rd, $rt",
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(DSLLV GPR64Opnd:$rd, GPR64Opnd:$rd, GPR32Opnd:$rt), 0>,
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ISA_MIPS3;
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def : MipsInstAlias<"dins $rt, $rs, $pos, $size",
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(DINSM GPR64Opnd:$rt, GPR64Opnd:$rs, uimm5:$pos,
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uimm_range_2_64:$size), 0>, ISA_MIPS64R2;
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def : MipsInstAlias<"dins $rt, $rs, $pos, $size",
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(DINSU GPR64Opnd:$rt, GPR64Opnd:$rs, uimm5_plus32:$pos,
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uimm5_plus1:$size), 0>, ISA_MIPS64R2;
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// Two operand (implicit 0 selector) versions:
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def : MipsInstAlias<"dmtc0 $rt, $rd",
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@ -883,7 +883,7 @@ def uimm16_altrelaxed : Operand<i32> {
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// Like uimm5 but reports a less confusing error for 32-63 when
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// an instruction alias permits that.
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def uimm5_report_uimm6 : Operand<i32> {
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let PrintMethod = "printUImm<5>";
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let PrintMethod = "printUImm<6>";
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let ParserMatchClass = ConstantUImm5ReportUImm6AsmOperandClass;
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}
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@ -189,8 +189,8 @@
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0x00 0x00 0x39 0x7c # CHECK: evp $zero
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0x00 0x00 0x43 0x7c # CHECK: tlbinv
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0x00 0x00 0x53 0x7c # CHECK: tlbinvf
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0x58 0x82 0x20 0x34 # CHECK: dinsu $4, $2, 32, 5
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0x58 0x82 0x38 0xc4 # CHECK: dinsm $4, $2, 3, 5
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0x58 0x82 0x20 0x34 # CHECK: dins $4, $2, 32, 5
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0x58 0x82 0x48 0xc4 # CHECK: dins $4, $2, 3, 39
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0x58 0x82 0x38 0xcc # CHECK: dins $4, $2, 3, 5
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0x00 0xa9 0x02 0xfc # CHECK: mtc0 $5, $9, 0
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0x00 0xa9 0x02 0xfc # CHECK: mtc0 $5, $9
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@ -34,7 +34,6 @@
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tne $8, $9, -1 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
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tne $8, $9, 16 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
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dins $2, $3, -1, 1 # CHECK: :[[@LINE]]:16: error: expected 6-bit unsigned immediate
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dins $2, $3, 32, 1 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
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syscall -1 # CHECK: :[[@LINE]]:11: error: expected 20-bit unsigned immediate
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syscall $4 # CHECK: :[[@LINE]]:11: error: expected 20-bit unsigned immediate
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syscall 1024 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
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@ -45,9 +45,7 @@
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dextu $2, $3, 64, 1 # CHECK: :[[@LINE]]:17: error: expected immediate in range 32 .. 63
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dextu $2, $3, 32, 0 # CHECK: :[[@LINE]]:21: error: expected immediate in range 1 .. 32
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dextu $2, $3, 32, 33 # CHECK: :[[@LINE]]:21: error: expected immediate in range 1 .. 32
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dins $2, $3, 31, 33 # CHECK: :[[@LINE]]:20: error: expected immediate in range 1 .. 32
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dins $2, $3, 31, 0 # CHECK: :[[@LINE]]:20: error: expected immediate in range 1 .. 32
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# FIXME: Check '32 <= pos + size <= 64' constraint on dinsm
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dinsm $2, $3, -1, 1 # CHECK: :[[@LINE]]:17: error: expected 5-bit unsigned immediate
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dinsm $2, $3, 32, 1 # CHECK: :[[@LINE]]:17: error: expected 5-bit unsigned immediate
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dinsm $2, $3, 31, 0 # CHECK: :[[@LINE]]:21: error: expected immediate in range 2 .. 64
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@ -198,7 +198,7 @@ a:
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tlbinv # CHECK: tlbinv # encoding: [0x00,0x00,0x43,0x7c]
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tlbinvf # CHECK: tlbinvf # encoding: [0x00,0x00,0x53,0x7c]
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dinsu $4, $2, 32, 5 # CHECK: dinsu $4, $2, 32, 5 # encoding: [0x58,0x82,0x20,0x34]
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dinsm $4, $2, 3, 5 # CHECK: dinsm $4, $2, 3, 5 # encoding: [0x58,0x82,0x38,0xc4]
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dinsm $4, $2, 31, 5 # CHECK: dinsm $4, $2, 31, 5 # encoding: [0x58,0x82,0x1f,0xc4]
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dins $4, $2, 3, 5 # CHECK: dins $4, $2, 3, 5 # encoding: [0x58,0x82,0x38,0xcc]
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lh $2, 8($4) # CHECK: lh $2, 8($4) # encoding: [0x3c,0x44,0x00,0x08]
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lhe $4, 8($2) # CHECK: lhe $4, 8($2) # encoding: [0x60,0x82,0x6a,0x08]
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@ -1,9 +1,25 @@
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# RUN: llvm-mc -arch=mips64el -filetype=obj -mcpu=mips64r2 -target-abi=n64 %s -o - \
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# RUN: | llvm-objdump -disassemble - | FileCheck %s
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# RUN: | llvm-objdump -disassemble - | FileCheck --check-prefix=OBJ %s
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# RUN: llvm-mc -arch=mips64el -filetype=obj -mcpu=mips64r6 -mattr=+micromips \
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# RUN: -target-abi=n64 %s -o - | llvm-objdump -disassemble - \
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# RUN: | FileCheck --check-prefix=OBJ %s
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dext $2, $4, 5, 10 # CHECK: dext ${{[0-9]+}}, ${{[0-9]+}}, 5, 10
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dextu $2, $4, 34, 6 # CHECK: dextu ${{[0-9]+}}, ${{[0-9]+}}, 34, 6
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dextm $2, $4, 5, 34 # CHECK: dextm ${{[0-9]+}}, ${{[0-9]+}}, 5, 34
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dins $4, $5, 8, 10 # CHECK: dins ${{[0-9]+}}, ${{[0-9]+}}, 8, 10
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dinsm $4, $5, 30, 6 # CHECK: dinsm ${{[0-9]+}}, ${{[0-9]+}}, 30, 6
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dinsu $4, $5, 40, 13 # CHECK: dinsu ${{[0-9]+}}, ${{[0-9]+}}, 40, 13
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# RUN: llvm-mc -arch=mips64el -mcpu=mips64r2 -target-abi=n64 %s -o - \
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# RUN: | FileCheck --check-prefix=ASM %s
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# RUN: llvm-mc -arch=mips64el -mcpu=mips64r6 -mattr=+micromips -target-abi=n64 \
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# RUN: %s -o - | FileCheck --check-prefix=ASM %s
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||||
|
||||
dext $2, $4, 5, 10 # OBJ: dext ${{[0-9]+}}, ${{[0-9]+}}, 5, 10
|
||||
dextu $2, $4, 34, 6 # OBJ: dextu ${{[0-9]+}}, ${{[0-9]+}}, 34, 6
|
||||
dextm $2, $4, 5, 34 # OBJ: dextm ${{[0-9]+}}, ${{[0-9]+}}, 5, 34
|
||||
dins $4, $5, 8, 10 # OBJ: dins ${{[0-9]+}}, ${{[0-9]+}}, 8, 10
|
||||
dinsm $4, $5, 30, 6 # OBJ: dins ${{[0-9]+}}, ${{[0-9]+}}, 30, 6
|
||||
dinsu $4, $5, 40, 13 # OBJ: dins ${{[0-9]+}}, ${{[0-9]+}}, 40, 13
|
||||
# check the aliases
|
||||
dins $2, $4, 5, 10 # OBJ: dins ${{[0-9]+}}, ${{[0-9]+}}, 5, 10
|
||||
dins $2, $4, 34, 6 # OBJ: dins ${{[0-9]+}}, ${{[0-9]+}}, 34, 6
|
||||
dins $2, $4, 5, 34 # OBJ: dins ${{[0-9]+}}, ${{[0-9]+}}, 5, 34
|
||||
# check the edge values
|
||||
dins $3, $4, 31, 1 # ASM: dins $3, $4, 31, 1
|
||||
dins $3, $4, 31, 33 # ASM: dinsm $3, $4, 31, 33
|
||||
dins $3, $4, 32, 32 # ASM: dinsu $3, $4, 32, 32
|
||||
|
||||
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Reference in New Issue
Block a user