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[X86][Haswell][SchedModel] Add architecture specific scheduling models.

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Group: Integer instructions.
Sub-group: Other instructions.

<rdar://problem/15607571>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215910 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Quentin Colombet 2014-08-18 17:55:23 +00:00
parent 184c0f8b2f
commit d2ea3168ae
1 changed files with 37 additions and 0 deletions
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37
lib/Target/X86/X86SchedHaswell.td
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@ -942,4 +942,41 @@ def WriteCMPXCHG16B : SchedWriteRes<[]> {
}
def : InstRW<[WriteCMPXCHG16B], (instregex "CMPXCHG16B")>;
//-- Other --//
// PAUSE.
def WritePAUSE : SchedWriteRes<[HWPort05, HWPort6]> {
let NumMicroOps = 5;
let ResourceCycles = [1, 3];
}
def : InstRW<[WritePAUSE], (instregex "PAUSE")>;
// LEAVE.
def : InstRW<[Write2P0156_P23], (instregex "LEAVE")>;
// XGETBV.
def WriteXGETBV : SchedWriteRes<[]> {
let NumMicroOps = 8;
}
def : InstRW<[WriteXGETBV], (instregex "XGETBV")>;
// RDTSC.
def WriteRDTSC : SchedWriteRes<[]> {
let NumMicroOps = 15;
}
def : InstRW<[WriteRDTSC], (instregex "RDTSC")>;
// RDPMC.
def WriteRDPMC : SchedWriteRes<[]> {
let NumMicroOps = 34;
}
def : InstRW<[WriteRDPMC], (instregex "RDPMC")>;
// RDRAND.
def WriteRDRAND : SchedWriteRes<[HWPort23, HWPort015]> {
let NumMicroOps = 17;
let ResourceCycles = [1, 16];
}
def : InstRW<[WriteRDRAND], (instregex "RDRAND(16|32|64)r")>;
} // SchedModel