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Avoid redundant select node in early if-conversion pass
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240072 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -479,11 +479,20 @@ void SSAIfConv::rewritePHIOperands() {
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// Convert all PHIs to select instructions inserted before FirstTerm.
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for (unsigned i = 0, e = PHIs.size(); i != e; ++i) {
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PHIInfo &PI = PHIs[i];
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unsigned DstReg = 0;
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DEBUG(dbgs() << "If-converting " << *PI.PHI);
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unsigned PHIDst = PI.PHI->getOperand(0).getReg();
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unsigned DstReg = MRI->createVirtualRegister(MRI->getRegClass(PHIDst));
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TII->insertSelect(*Head, FirstTerm, HeadDL, DstReg, Cond, PI.TReg, PI.FReg);
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DEBUG(dbgs() << " --> " << *std::prev(FirstTerm));
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if (PI.TReg == PI.FReg) {
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// We do not need the select instruction if both incoming values are
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// equal.
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DstReg = PI.TReg;
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} else {
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unsigned PHIDst = PI.PHI->getOperand(0).getReg();
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DstReg = MRI->createVirtualRegister(MRI->getRegClass(PHIDst));
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TII->insertSelect(*Head, FirstTerm, HeadDL,
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DstReg, Cond, PI.TReg, PI.FReg);
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DEBUG(dbgs() << " --> " << *std::prev(FirstTerm));
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}
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// Rewrite PHI operands TPred -> (DstReg, Head), remove FPred.
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for (unsigned i = PI.PHI->getNumOperands(); i != 1; i -= 2) {
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41
test/CodeGen/AArch64/ifcvt-select.ll
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41
test/CodeGen/AArch64/ifcvt-select.ll
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@ -0,0 +1,41 @@
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; RUN: llc -mtriple=arm64-apple-ios -mcpu=cyclone < %s | FileCheck %s
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; Do not generate redundant select in early if-converstion pass.
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define i32 @foo(i32 %a, i32 %b) {
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entry:
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;CHECK-LABEL: foo:
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;CHECK: csinc
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;CHECK-NOT: csel
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%sub = sub nsw i32 %b, %a
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%cmp10 = icmp sgt i32 %a, 0
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br i1 %cmp10, label %while.body.lr.ph, label %while.end
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while.body.lr.ph:
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br label %while.body
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while.body:
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%j.012 = phi i32 [ %sub, %while.body.lr.ph ], [ %inc, %if.then ], [ %inc, %if.else ]
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%i.011 = phi i32 [ %a, %while.body.lr.ph ], [ %inc2, %if.then ], [ %dec, %if.else ]
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%cmp1 = icmp slt i32 %i.011, %j.012
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br i1 %cmp1, label %while.end, label %while.cond
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while.cond:
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%inc = add nsw i32 %j.012, 5
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%cmp2 = icmp slt i32 %inc, %b
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br i1 %cmp2, label %if.then, label %if.else
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if.then:
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%inc2 = add nsw i32 %i.011, 1
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br label %while.body
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if.else:
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%dec = add nsw i32 %i.011, -1
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br label %while.body
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while.end:
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%j.0.lcssa = phi i32 [ %j.012, %while.body ], [ %sub, %entry ]
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%i.0.lcssa = phi i32 [ %i.011, %while.body ], [ %a, %entry ]
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%add = add nsw i32 %j.0.lcssa, %i.0.lcssa
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ret i32 %add
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}
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