[RegisterBankInfo] Add dump/print methods for OperandsMapper.

Improve debuggability of the OperandsMapper helper class.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272207 91177308-0d34-0410-b5e6-96231b3b80d8

include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h

@@ -262,10 +262,19 @@ public:
     /// called.
     /// The iterator may be invalidated by a call to setVRegs or createVRegs.
     ///
+    /// When \p ForDebug is true, we will not check that the list of new virtual
+    /// registers does not contain uninitialized values.
+    ///
     /// \pre getMI().getOperand(OpIdx).isReg()
-    /// \pre All partial mappings have been set a register
+    /// \pre ForDebug || All partial mappings have been set a register
     iterator_range<SmallVectorImpl<unsigned>::const_iterator>
-    getVRegs(unsigned OpIdx) const;
+    getVRegs(unsigned OpIdx, bool ForDebug = false) const;
+
+    /// Print this operands mapper on dbgs() stream.
+    void dump() const;
+
+    /// Print this operands mapper on \p OS stream.
+    void print(raw_ostream &OS, bool ForDebug = false) const;
   };
 
 protected:
@@ -574,6 +583,12 @@ operator<<(raw_ostream &OS,
   InstrMapping.print(OS);
   return OS;
 }
+
+inline raw_ostream &
+operator<<(raw_ostream &OS, const RegisterBankInfo::OperandsMapper &OpdMapper) {
+  OpdMapper.print(OS, /*ForDebug*/ false);
+  return OS;
+}
 } // End namespace llvm.
 
 #endif

lib/CodeGen/GlobalISel/RegisterBankInfo.cpp

@@ -576,7 +576,9 @@ void RegisterBankInfo::OperandsMapper::setVRegs(unsigned OpIdx,
 }
 
 iterator_range<SmallVectorImpl<unsigned>::const_iterator>
-RegisterBankInfo::OperandsMapper::getVRegs(unsigned OpIdx) const {
+RegisterBankInfo::OperandsMapper::getVRegs(unsigned OpIdx,
+                                           bool ForDebug) const {
+  (void)ForDebug;
   assert(OpIdx < getMI().getNumOperands() && "Out-of-bound access");
   int StartIdx = OpToNewVRegIdx[OpIdx];
 
@@ -593,7 +595,58 @@ RegisterBankInfo::OperandsMapper::getVRegs(unsigned OpIdx) const {
       make_range(&NewVRegs[StartIdx], End);
 #ifndef NDEBUG
   for (unsigned VReg : Res)
-    assert(VReg && "Some registers are uninitialized");
+    assert((VReg || ForDebug) && "Some registers are uninitialized");
 #endif
   return Res;
 }
+
+void RegisterBankInfo::OperandsMapper::dump() const {
+  print(dbgs(), true);
+  dbgs() << '\n';
+}
+
+void RegisterBankInfo::OperandsMapper::print(raw_ostream &OS,
+                                             bool ForDebug) const {
+  unsigned NumOpds = getMI().getNumOperands();
+  if (ForDebug) {
+    OS << "Mapping for " << getMI() << "\nwith " << getInstrMapping() << '\n';
+    // Print out the internal state of the index table.
+    OS << "Populated indices (CellNumber, IndexInNewVRegs): ";
+    bool IsFirst = true;
+    for (unsigned Idx = 0; Idx != NumOpds; ++Idx) {
+      if (OpToNewVRegIdx[Idx] != DontKnowIdx) {
+        if (!IsFirst)
+          OS << ", ";
+        OS << '(' << Idx << ", " << OpToNewVRegIdx[Idx] << ')';
+        IsFirst = false;
+      }
+    }
+    OS << '\n';
+  } else
+    OS << "Mapping ID: " << getInstrMapping().getID() << ' ';
+
+  OS << "Operand Mapping: ";
+  // If we have a function, we can pretty print the name of the registers.
+  // Otherwise we will print the raw numbers.
+  const TargetRegisterInfo *TRI =
+      getMI().getParent() && getMI().getParent()->getParent()
+          ? getMI().getParent()->getParent()->getSubtarget().getRegisterInfo()
+          : nullptr;
+  bool IsFirst = true;
+  for (unsigned Idx = 0; Idx != NumOpds; ++Idx) {
+    if (OpToNewVRegIdx[Idx] == DontKnowIdx)
+      continue;
+    if (!IsFirst)
+      OS << ", ";
+    IsFirst = false;
+    OS << '(' << PrintReg(getMI().getOperand(Idx).getReg(), TRI) << ", [";
+    bool IsFirstNewVReg = true;
+    for (unsigned VReg : getVRegs(Idx)) {
+      if (!IsFirstNewVReg)
+        OS << ", ";
+      IsFirstNewVReg = false;
+      OS << PrintReg(VReg, TRI);
+    }
+    OS << "])";
+  }
+}