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Add a new MachineInstr-level DCE pass. It is very simple, and is intended to
be used with fast-isel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56268 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -29,6 +29,8 @@ namespace {
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if (std::getenv("bar") != (char*) -1)
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return;
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(void) llvm::createDeadMachineInstructionElimPass();
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(void) llvm::createSimpleRegisterAllocator();
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(void) llvm::createLocalRegisterAllocator();
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(void) llvm::createBigBlockRegisterAllocator();
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@ -75,6 +75,11 @@ namespace llvm {
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/// machine basic blocks.
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extern const PassInfo *const UnreachableMachineBlockElimID;
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/// DeadMachineInstructionElim pass - This pass removes dead machine
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/// instructions.
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///
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FunctionPass *createDeadMachineInstructionElimPass();
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/// Creates a register allocator as the user specified on the command line.
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///
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FunctionPass *createRegisterAllocator();
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99
lib/CodeGen/DeadMachineInstructionElim.cpp
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99
lib/CodeGen/DeadMachineInstructionElim.cpp
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@ -0,0 +1,99 @@
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//===- DeadMachineInstructionElim.cpp - Remove dead machine instructions --===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This is an extremely simple MachineInstr-level dead-code-elimination pass.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Pass.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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using namespace llvm;
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namespace {
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class VISIBILITY_HIDDEN DeadMachineInstructionElim :
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public MachineFunctionPass {
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virtual bool runOnMachineFunction(MachineFunction &MF);
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public:
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static char ID; // Pass identification, replacement for typeid
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DeadMachineInstructionElim() : MachineFunctionPass(&ID) {}
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};
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}
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char DeadMachineInstructionElim::ID = 0;
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static RegisterPass<DeadMachineInstructionElim>
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Y("dead-mi-elimination",
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"Remove dead machine instructions");
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FunctionPass *llvm::createDeadMachineInstructionElimPass() {
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return new DeadMachineInstructionElim();
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}
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bool DeadMachineInstructionElim::runOnMachineFunction(MachineFunction &MF) {
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bool AnyChanges = false;
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const MachineRegisterInfo &MRI = MF.getRegInfo();
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const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
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bool SawStore = true;
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// Loop over all instructions in all blocks, from bottom to top, so that it's
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// more likely that chains of dependent but ultimately dead instructions will
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// be cleaned up.
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for (MachineFunction::reverse_iterator I = MF.rbegin(), E = MF.rend();
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I != E; ++I) {
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MachineBasicBlock *MBB = &*I;
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for (MachineBasicBlock::reverse_iterator MII = MBB->rbegin(),
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MIE = MBB->rend(); MII != MIE; ) {
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MachineInstr *MI = &*MII;
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// Don't delete instructions with side effects.
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if (MI->isSafeToMove(&TII, SawStore)) {
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// Examine each operand.
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bool AllDefsDead = true;
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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if (MO.isRegister() && MO.isDef()) {
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unsigned Reg = MO.getReg();
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if (TargetRegisterInfo::isPhysicalRegister(Reg) ||
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!MRI.use_empty(Reg)) {
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// This def has a use. Don't delete the instruction!
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AllDefsDead = false;
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break;
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}
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}
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}
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// If there are no defs with uses, the instruction is dead.
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if (AllDefsDead) {
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// Clear out the operands to take the registers out of their
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// use chains.
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while (unsigned Num = MI->getNumOperands())
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MI->RemoveOperand(Num-1);
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// Delete the actual instruction.
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AnyChanges = true;
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MI->eraseFromParent();
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MIE = MBB->rend();
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// MII is now pointing to the next instruction to process,
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// so don't increment it.
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continue;
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}
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}
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// We didn't delete the current instruction, so increment MII to
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// the next one.
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++MII;
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}
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}
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return AnyChanges;
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}
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