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[mips] Add PredicateControl to InstAlias's
Summary: No functional change Depends on D3649 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3672 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208334 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Sanders
parent
a37c8c026d
commit
d41a985f33
@ -296,5 +296,5 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
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//===----------------------------------------------------------------------===//
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let Predicates = [InMicroMips] in {
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def : InstAlias<"wait", (WAIT_MM 0x0), 1>;
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def : MipsInstAlias<"wait", (WAIT_MM 0x0), 1>;
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}
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@ -418,40 +418,42 @@ def : MipsPat<(bswap GPR64:$rt), (DSHD (DSBH GPR64:$rt))>;
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//===----------------------------------------------------------------------===//
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// Instruction aliases
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//===----------------------------------------------------------------------===//
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def : InstAlias<"move $dst, $src",
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(DADDu GPR64Opnd:$dst, GPR64Opnd:$src, ZERO_64), 1>,
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def : MipsInstAlias<"move $dst, $src",
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(DADDu GPR64Opnd:$dst, GPR64Opnd:$src, ZERO_64), 1>,
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Requires<[IsGP64]>;
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def : InstAlias<"daddu $rs, $rt, $imm",
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(DADDiu GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm),
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0>;
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def : InstAlias<"dadd $rs, $rt, $imm",
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(DADDi GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm),
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0>;
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def : InstAlias<"daddu $rs, $imm",
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(DADDiu GPR64Opnd:$rs, GPR64Opnd:$rs, simm16_64:$imm),
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0>;
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def : InstAlias<"dadd $rs, $imm",
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(DADDi GPR64Opnd:$rs, GPR64Opnd:$rs, simm16_64:$imm),
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0>;
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def : InstAlias<"add $rs, $imm",
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(ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm),
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0>;
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def : InstAlias<"addu $rs, $imm",
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(ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm),
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0>;
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def : InstAlias<"dsll $rd, $rt, $rs",
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(DSLLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>;
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def : InstAlias<"dsubu $rt, $rs, $imm",
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(DADDiu GPR64Opnd:$rt, GPR64Opnd:$rs,
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InvertedImOperand64: $imm),0>;
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def : InstAlias<"dsub $rs, $imm",
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(DADDi GPR64Opnd:$rs, GPR64Opnd:$rs, InvertedImOperand64:$imm),
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0>;
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def : InstAlias<"dsubu $rs, $imm",
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(DADDiu GPR64Opnd:$rs, GPR64Opnd:$rs, InvertedImOperand64:$imm),
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0>;
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def : InstAlias<"dsrl $rd, $rt, $rs",
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(DSRLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>;
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def : MipsInstAlias<"daddu $rs, $rt, $imm",
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(DADDiu GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm),
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0>;
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def : MipsInstAlias<"dadd $rs, $rt, $imm",
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(DADDi GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm),
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0>;
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def : MipsInstAlias<"daddu $rs, $imm",
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(DADDiu GPR64Opnd:$rs, GPR64Opnd:$rs, simm16_64:$imm),
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0>;
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def : MipsInstAlias<"dadd $rs, $imm",
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(DADDi GPR64Opnd:$rs, GPR64Opnd:$rs, simm16_64:$imm),
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0>;
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def : MipsInstAlias<"add $rs, $imm",
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(ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm),
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0>;
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def : MipsInstAlias<"addu $rs, $imm",
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(ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm),
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0>;
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def : MipsInstAlias<"dsll $rd, $rt, $rs",
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(DSLLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>;
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def : MipsInstAlias<"dsubu $rt, $rs, $imm",
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(DADDiu GPR64Opnd:$rt, GPR64Opnd:$rs,
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InvertedImOperand64:$imm), 0>;
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def : MipsInstAlias<"dsub $rs, $imm",
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(DADDi GPR64Opnd:$rs, GPR64Opnd:$rs,
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InvertedImOperand64:$imm),
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0>;
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def : MipsInstAlias<"dsubu $rs, $imm",
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(DADDiu GPR64Opnd:$rs, GPR64Opnd:$rs,
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InvertedImOperand64:$imm),
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0>;
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def : MipsInstAlias<"dsrl $rd, $rt, $rs",
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(DSRLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>;
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/// Move between CPU and coprocessor registers
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let DecoderNamespace = "Mips64", Predicates = [HasMips64] in {
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@ -462,8 +464,8 @@ def DMTC2 : MFC3OP<"dmtc2", GPR64Opnd>, MFC3OP_FM<0x12, 5>;
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}
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// Two operand (implicit 0 selector) versions:
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def : InstAlias<"dmfc0 $rt, $rd", (DMFC0 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;
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def : InstAlias<"dmtc0 $rt, $rd", (DMTC0 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;
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def : InstAlias<"dmfc2 $rt, $rd", (DMFC2 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;
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def : InstAlias<"dmtc2 $rt, $rd", (DMTC2 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;
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def : MipsInstAlias<"dmfc0 $rt, $rd", (DMFC0 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;
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def : MipsInstAlias<"dmtc0 $rt, $rd", (DMTC0 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;
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def : MipsInstAlias<"dmfc2 $rt, $rd", (DMFC2 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;
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def : MipsInstAlias<"dmtc2 $rt, $rd", (DMTC2 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;
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@ -565,8 +565,8 @@ def ExtractElementF64_64 : ExtractElementF64Base<FGR64Opnd>,
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//===----------------------------------------------------------------------===//
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// InstAliases.
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//===----------------------------------------------------------------------===//
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def : InstAlias<"bc1t $offset", (BC1T FCC0, brtarget:$offset)>;
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def : InstAlias<"bc1f $offset", (BC1F FCC0, brtarget:$offset)>;
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def : MipsInstAlias<"bc1t $offset", (BC1T FCC0, brtarget:$offset)>;
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def : MipsInstAlias<"bc1f $offset", (BC1F FCC0, brtarget:$offset)>;
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//===----------------------------------------------------------------------===//
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// Floating Point Patterns
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@ -221,6 +221,9 @@ class MipsPat<dag pattern, dag result> : Pat<pattern, result>, PredicateControl
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let EncodingPredicates = [HasStdEnc];
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}
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class MipsInstAlias<string Asm, dag Result, bit Emit = 0b1> :
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InstAlias<Asm, Result, Emit>, PredicateControl;
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class IsCommutable {
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bit isCommutable = 1;
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}
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@ -1220,75 +1223,78 @@ def TLBWR : TLB<"tlbwr">, COP0_TLB_FM<0x06>;
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//===----------------------------------------------------------------------===//
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// Instruction aliases
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//===----------------------------------------------------------------------===//
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def : InstAlias<"move $dst, $src",
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(ADDu GPR32Opnd:$dst, GPR32Opnd:$src,ZERO), 1>,
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def : MipsInstAlias<"move $dst, $src",
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(ADDu GPR32Opnd:$dst, GPR32Opnd:$src,ZERO), 1>,
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Requires<[IsGP32, NotInMicroMips]>;
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def : InstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>;
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def : InstAlias<"addu $rs, $rt, $imm",
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(ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
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def : InstAlias<"add $rs, $rt, $imm",
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(ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
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def : InstAlias<"and $rs, $rt, $imm",
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(ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
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def : InstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>;
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def : MipsInstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>;
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def : MipsInstAlias<"addu $rs, $rt, $imm",
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(ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
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def : MipsInstAlias<"add $rs, $rt, $imm",
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(ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
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def : MipsInstAlias<"and $rs, $rt, $imm",
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(ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
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def : MipsInstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>;
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let Predicates = [NotInMicroMips] in {
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def : InstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>;
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def : MipsInstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>;
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}
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def : InstAlias<"jal $rs", (JALR RA, GPR32Opnd:$rs), 0>;
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def : InstAlias<"jal $rd,$rs", (JALR GPR32Opnd:$rd, GPR32Opnd:$rs), 0>;
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def : InstAlias<"not $rt, $rs",
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(NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>;
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def : InstAlias<"neg $rt, $rs",
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(SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
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def : InstAlias<"negu $rt",
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(SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 0>;
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def : InstAlias<"negu $rt, $rs",
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(SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
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def : InstAlias<"slt $rs, $rt, $imm",
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(SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
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def : InstAlias<"sltu $rt, $rs, $imm",
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(SLTiu GPR32Opnd:$rt, GPR32Opnd:$rs, simm16:$imm), 0>;
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def : InstAlias<"xor $rs, $rt, $imm",
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(XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
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def : InstAlias<"or $rs, $rt, $imm",
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(ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
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def : InstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
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def : InstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
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def : InstAlias<"mtc0 $rt, $rd", (MTC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
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def : InstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
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def : InstAlias<"mtc2 $rt, $rd", (MTC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
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def : InstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>;
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def : InstAlias<"bnez $rs,$offset",
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(BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
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def : InstAlias<"beqz $rs,$offset",
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(BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
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def : InstAlias<"syscall", (SYSCALL 0), 1>;
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def : MipsInstAlias<"jal $rs", (JALR RA, GPR32Opnd:$rs), 0>;
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def : MipsInstAlias<"jal $rd,$rs", (JALR GPR32Opnd:$rd, GPR32Opnd:$rs), 0>;
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def : MipsInstAlias<"not $rt, $rs",
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(NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>;
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def : MipsInstAlias<"neg $rt, $rs",
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(SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
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def : MipsInstAlias<"negu $rt",
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(SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 0>;
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def : MipsInstAlias<"negu $rt, $rs",
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(SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
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def : MipsInstAlias<"slt $rs, $rt, $imm",
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(SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
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def : MipsInstAlias<"sltu $rt, $rs, $imm",
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(SLTiu GPR32Opnd:$rt, GPR32Opnd:$rs, simm16:$imm), 0>;
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def : MipsInstAlias<"xor $rs, $rt, $imm",
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(XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
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def : MipsInstAlias<"or $rs, $rt, $imm",
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(ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
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def : MipsInstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
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def : MipsInstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
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def : MipsInstAlias<"mtc0 $rt, $rd", (MTC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
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def : MipsInstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
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def : MipsInstAlias<"mtc2 $rt, $rd", (MTC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
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def : MipsInstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>;
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def : MipsInstAlias<"bnez $rs,$offset",
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(BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
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def : MipsInstAlias<"beqz $rs,$offset",
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(BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
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def : MipsInstAlias<"syscall", (SYSCALL 0), 1>;
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def : MipsInstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
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def : MipsInstAlias<"break", (BREAK 0, 0), 1>;
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def : MipsInstAlias<"ei", (EI ZERO), 1>;
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def : MipsInstAlias<"di", (DI ZERO), 1>;
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def : InstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
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def : InstAlias<"break", (BREAK 0, 0), 1>;
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def : InstAlias<"ei", (EI ZERO), 1>;
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def : InstAlias<"di", (DI ZERO), 1>;
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def : InstAlias<"teq $rs, $rt", (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
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def : InstAlias<"tge $rs, $rt", (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
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def : InstAlias<"tgeu $rs, $rt", (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
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def : InstAlias<"tlt $rs, $rt", (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
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def : InstAlias<"tltu $rs, $rt", (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
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def : InstAlias<"tne $rs, $rt", (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
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def : InstAlias<"sll $rd, $rt, $rs",
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(SLLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
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def : InstAlias<"sub, $rd, $rs, $imm",
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(ADDi GPR32Opnd:$rd, GPR32Opnd:$rs, InvertedImOperand:$imm)>;
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def : InstAlias<"sub $rs, $imm",
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(ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, InvertedImOperand:$imm),
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0>;
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def : InstAlias<"subu, $rd, $rs, $imm",
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(ADDiu GPR32Opnd:$rd, GPR32Opnd:$rs, InvertedImOperand:$imm)>;
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def : InstAlias<"subu $rs, $imm",
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(ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs, InvertedImOperand:$imm),
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0>;
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def : InstAlias<"srl $rd, $rt, $rs",
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(SRLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
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def : MipsInstAlias<"teq $rs, $rt", (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
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def : MipsInstAlias<"tge $rs, $rt", (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
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def : MipsInstAlias<"tgeu $rs, $rt", (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0),
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1>;
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def : MipsInstAlias<"tlt $rs, $rt", (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
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def : MipsInstAlias<"tltu $rs, $rt", (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0),
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1>;
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def : MipsInstAlias<"tne $rs, $rt", (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
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def : MipsInstAlias<"sll $rd, $rt, $rs",
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(SLLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
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def : MipsInstAlias<"sub, $rd, $rs, $imm",
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(ADDi GPR32Opnd:$rd, GPR32Opnd:$rs,
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InvertedImOperand:$imm)>;
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def : MipsInstAlias<"sub $rs, $imm",
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(ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, InvertedImOperand:$imm),
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0>;
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def : MipsInstAlias<"subu, $rd, $rs, $imm",
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(ADDiu GPR32Opnd:$rd, GPR32Opnd:$rs,
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InvertedImOperand:$imm)>;
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def : MipsInstAlias<"subu $rs, $imm", (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs,
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InvertedImOperand:$imm), 0>;
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def : MipsInstAlias<"srl $rd, $rt, $rs",
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(SRLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
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//===----------------------------------------------------------------------===//
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// Assembler Pseudo Instructions
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//===----------------------------------------------------------------------===//
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