RPCS3/llvm
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm.git synced 2025-02-26 05:36:36 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

[SDAG] Fix visitAND optimization to deal with vector extract case again.

Browse Source 
Summary:
Fix case elided by rL298920.

Fixes PR32545.

Reviewers: eli.friedman, RKSimon

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D31759

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@299688 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nirav Dave 2017-04-06 19:05:41 +00:00
parent f8e400cffa
commit d4d2ab353e
2 changed files with 23 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -3589,7 +3589,7 @@ SDValue DAGCombiner::visitAND(SDNode *N) {
SDValue NewLoad(Load, 0);
// Fold the AND away. NewLoad may get replaced immediately.
CombineTo(N, NewLoad);
CombineTo(N, (N0.getNode() == Load) ? NewLoad : N0);
if (Load->getExtensionType() == ISD::EXTLOAD) {
NewLoad = DAG.getLoad(Load->getAddressingMode(), ISD::ZEXTLOAD,

22
test/CodeGen/ARM/pr32545.ll Normal file
View File

@ -0,0 +1,22 @@
; RUN: llc %s -o - | FileCheck %s
target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "armv7--linux-gnueabi"
; CHECK: vld1.16 {[[DREG:d[0-9]+]][0]}, {{.*}}
; CHECK: vmovl.u8 [[QREG:q[0-9]+]], [[DREG]]
; CHECK: vmovl.u16 [[QREG]], [[DREG]]
define void @f(i32 %dstStride, i8* %indvars.iv, <2 x i8>* %zz) {
entry:
br label %for.body
for.body:
%tmp = load <2 x i8>, <2 x i8>* %zz, align 1
%tmp1 = extractelement <2 x i8> %tmp, i32 0
%.lhs.rhs = zext i8 %tmp1 to i32
call void @g(i32 %.lhs.rhs)
br label %for.body
}
declare void @g(i32)