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Add [reg+reg] integer stores

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24789 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2005-12-17 20:44:36 +00:00
parent d30a630636
commit d55e1ca5ef
2 changed files with 30 additions and 0 deletions
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15
lib/Target/Sparc/SparcInstrInfo.td
View File

@ -173,18 +173,33 @@ def LDDFri : F3_2<3, 0b100011,
[(set DFPRegs:$dst, (load ADDRri:$addr))]>; [(set DFPRegs:$dst, (load ADDRri:$addr))]>;
// Section B.4 - Store Integer Instructions, p. 95 // Section B.4 - Store Integer Instructions, p. 95
def STBrr : F3_1<3, 0b000101,
(ops MEMrr:$addr, IntRegs:$src),
"stb $src, [$addr]",
[(truncstore IntRegs:$src, ADDRrr:$addr, i8)]>;
def STBri : F3_2<3, 0b000101, def STBri : F3_2<3, 0b000101,
(ops MEMri:$addr, IntRegs:$src), (ops MEMri:$addr, IntRegs:$src),
"stb $src, [$addr]", "stb $src, [$addr]",
[(truncstore IntRegs:$src, ADDRri:$addr, i8)]>; [(truncstore IntRegs:$src, ADDRri:$addr, i8)]>;
def STHrr : F3_1<3, 0b000110,
(ops MEMrr:$addr, IntRegs:$src),
"sth $src, [$addr]",
[(truncstore IntRegs:$src, ADDRrr:$addr, i16)]>;
def STHri : F3_2<3, 0b000110, def STHri : F3_2<3, 0b000110,
(ops MEMri:$addr, IntRegs:$src), (ops MEMri:$addr, IntRegs:$src),
"sth $src, [$addr]", "sth $src, [$addr]",
[(truncstore IntRegs:$src, ADDRri:$addr, i16)]>; [(truncstore IntRegs:$src, ADDRri:$addr, i16)]>;
def STrr : F3_1<3, 0b000100,
(ops MEMrr:$addr, IntRegs:$src),
"st $src, [$addr]",
[(store IntRegs:$src, ADDRrr:$addr)]>;
def STri : F3_2<3, 0b000100, def STri : F3_2<3, 0b000100,
(ops MEMri:$addr, IntRegs:$src), (ops MEMri:$addr, IntRegs:$src),
"st $src, [$addr]", "st $src, [$addr]",
[(store IntRegs:$src, ADDRri:$addr)]>; [(store IntRegs:$src, ADDRri:$addr)]>;
def STDrr : F3_1<3, 0b000111,
(ops MEMrr:$addr, IntRegs:$src),
"std $src, [$addr]", []>;
def STDri : F3_2<3, 0b000111, def STDri : F3_2<3, 0b000111,
(ops MEMri:$addr, IntRegs:$src), (ops MEMri:$addr, IntRegs:$src),
"std $src, [$addr]", []>; "std $src, [$addr]", []>;

15
lib/Target/SparcV8/SparcV8InstrInfo.td
View File

@ -173,18 +173,33 @@ def LDDFri : F3_2<3, 0b100011,
[(set DFPRegs:$dst, (load ADDRri:$addr))]>; [(set DFPRegs:$dst, (load ADDRri:$addr))]>;
// Section B.4 - Store Integer Instructions, p. 95 // Section B.4 - Store Integer Instructions, p. 95
def STBrr : F3_1<3, 0b000101,
(ops MEMrr:$addr, IntRegs:$src),
"stb $src, [$addr]",
[(truncstore IntRegs:$src, ADDRrr:$addr, i8)]>;
def STBri : F3_2<3, 0b000101, def STBri : F3_2<3, 0b000101,
(ops MEMri:$addr, IntRegs:$src), (ops MEMri:$addr, IntRegs:$src),
"stb $src, [$addr]", "stb $src, [$addr]",
[(truncstore IntRegs:$src, ADDRri:$addr, i8)]>; [(truncstore IntRegs:$src, ADDRri:$addr, i8)]>;
def STHrr : F3_1<3, 0b000110,
(ops MEMrr:$addr, IntRegs:$src),
"sth $src, [$addr]",
[(truncstore IntRegs:$src, ADDRrr:$addr, i16)]>;
def STHri : F3_2<3, 0b000110, def STHri : F3_2<3, 0b000110,
(ops MEMri:$addr, IntRegs:$src), (ops MEMri:$addr, IntRegs:$src),
"sth $src, [$addr]", "sth $src, [$addr]",
[(truncstore IntRegs:$src, ADDRri:$addr, i16)]>; [(truncstore IntRegs:$src, ADDRri:$addr, i16)]>;
def STrr : F3_1<3, 0b000100,
(ops MEMrr:$addr, IntRegs:$src),
"st $src, [$addr]",
[(store IntRegs:$src, ADDRrr:$addr)]>;
def STri : F3_2<3, 0b000100, def STri : F3_2<3, 0b000100,
(ops MEMri:$addr, IntRegs:$src), (ops MEMri:$addr, IntRegs:$src),
"st $src, [$addr]", "st $src, [$addr]",
[(store IntRegs:$src, ADDRri:$addr)]>; [(store IntRegs:$src, ADDRri:$addr)]>;
def STDrr : F3_1<3, 0b000111,
(ops MEMrr:$addr, IntRegs:$src),
"std $src, [$addr]", []>;
def STDri : F3_2<3, 0b000111, def STDri : F3_2<3, 0b000111,
(ops MEMri:$addr, IntRegs:$src), (ops MEMri:$addr, IntRegs:$src),
"std $src, [$addr]", []>; "std $src, [$addr]", []>;