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[RISCV] Mark FREM as Expand

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Mark the FREM SelectionDAG node as Expand, which is necessary in order to 
support the frem IR instruction on RISC-V. This is expanded into a library 
call. Adds the corresponding test. Previously, this would have triggered an 
assertion at instruction selection time.

Differential Revision: https://reviews.llvm.org/D54159
Patch by Luís Marques.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346958 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Alex Bradbury 2018-11-15 14:46:11 +00:00
parent 5ba6366a24
commit d566da724a
3 changed files with 33 additions and 1 deletions
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2
lib/Target/RISCV/RISCVISelLowering.cpp
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@ -114,7 +114,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
// TODO: add proper support for the various FMA variants
// (FMADD.S, FMSUB.S, FNMSUB.S, FNMADD.S).
ISD::NodeType FPOpToExtend[] = {
ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FMA};
ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FMA, ISD::FREM};
if (Subtarget.hasStdExtF()) {
setOperationAction(ISD::FMINNUM, MVT::f32, Legal);

16
test/CodeGen/RISCV/double-frem.ll Normal file
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@ -0,0 +1,16 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32ID %s
define double @frem_f64(double %a, double %b) nounwind {
; RV32ID-LABEL: frem_f64:
; RV32ID: # %bb.0:
; RV32ID-NEXT: addi sp, sp, -16
; RV32ID-NEXT: sw ra, 12(sp)
; RV32ID-NEXT: call fmod
; RV32ID-NEXT: lw ra, 12(sp)
; RV32ID-NEXT: addi sp, sp, 16
; RV32ID-NEXT: ret
%1 = frem double %a, %b
ret double %1
}

16
test/CodeGen/RISCV/float-frem.ll Normal file
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@ -0,0 +1,16 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IF %s
define float @frem_f32(float %a, float %b) nounwind {
; RV32IF-LABEL: frem_f32:
; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp)
; RV32IF-NEXT: call fmodf
; RV32IF-NEXT: lw ra, 12(sp)
; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret
%1 = frem float %a, %b
ret float %1
}