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PTX: Add new patterns for bitconvert and any_extend
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140753 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Justin Holewinski
parent
75c4abacaa
commit
d57c1bc0b6
@ -333,7 +333,7 @@ multiclass PTX_SETP_I<RegisterClass RC, string regclsname, Operand immcls,
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(not RegPred:$c)))]>;
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}
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multiclass PTX_SETP_FP<RegisterClass RC, string regclsname,
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multiclass PTX_SETP_FP<RegisterClass RC, string regclsname, Operand immcls,
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CondCode ucmp, CondCode ocmp, string cmpstr> {
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// TODO support 5-operand format: p|q, a, b, c
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@ -346,6 +346,15 @@ multiclass PTX_SETP_FP<RegisterClass RC, string regclsname,
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!strconcat("setp.", cmpstr, ".", regclsname, "\t$p, $a, $b"),
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[(set RegPred:$p, (setcc RC:$a, RC:$b, ocmp))]>;
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def ri_u
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: InstPTX<(outs RegPred:$p), (ins RC:$a, immcls:$b),
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!strconcat("setp.", cmpstr, "u.", regclsname, "\t$p, $a, $b"),
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[(set RegPred:$p, (setcc RC:$a, fpimm:$b, ucmp))]>;
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def ri_o
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: InstPTX<(outs RegPred:$p), (ins RC:$a, immcls:$b),
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!strconcat("setp.", cmpstr, ".", regclsname, "\t$p, $a, $b"),
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[(set RegPred:$p, (setcc RC:$a, fpimm:$b, ocmp))]>;
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def rr_and_r_u
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: InstPTX<(outs RegPred:$p), (ins RC:$a, RC:$b, RegPred:$c),
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!strconcat("setp.", cmpstr, "u.and.", regclsname,
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@ -423,11 +432,20 @@ multiclass PTX_SETP_FP<RegisterClass RC, string regclsname,
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(not RegPred:$c)))]>;
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}
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multiclass PTX_SELP<RegisterClass RC, string regclsname> {
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multiclass PTX_SELP<RegisterClass RC, string regclsname, Operand immcls,
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SDNode immnode> {
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def rr
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: InstPTX<(outs RC:$r), (ins RegPred:$a, RC:$b, RC:$c),
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!strconcat("selp.", regclsname, "\t$r, $b, $c, $a"),
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[(set RC:$r, (select RegPred:$a, RC:$b, RC:$c))]>;
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def ri
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: InstPTX<(outs RC:$r), (ins RegPred:$a, RC:$b, immcls:$c),
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!strconcat("selp.", regclsname, "\t$r, $b, $c, $a"),
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[(set RC:$r, (select RegPred:$a, RC:$b, immnode:$c))]>;
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def ii
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: InstPTX<(outs RC:$r), (ins RegPred:$a, immcls:$b, immcls:$c),
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!strconcat("selp.", regclsname, "\t$r, $b, $c, $a"),
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[(set RC:$r, (select RegPred:$a, immnode:$b, immnode:$c))]>;
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}
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@ -597,29 +615,29 @@ defm SETPGEs64 : PTX_SETP_I<RegI64, "s64", i64imm, SETGE, "ge">;
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// Compare f32
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defm SETPEQf32 : PTX_SETP_FP<RegF32, "f32", SETUEQ, SETOEQ, "eq">;
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defm SETPNEf32 : PTX_SETP_FP<RegF32, "f32", SETUNE, SETONE, "ne">;
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defm SETPLTf32 : PTX_SETP_FP<RegF32, "f32", SETULT, SETOLT, "lt">;
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defm SETPLEf32 : PTX_SETP_FP<RegF32, "f32", SETULE, SETOLE, "le">;
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defm SETPGTf32 : PTX_SETP_FP<RegF32, "f32", SETUGT, SETOGT, "gt">;
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defm SETPGEf32 : PTX_SETP_FP<RegF32, "f32", SETUGE, SETOGE, "ge">;
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defm SETPEQf32 : PTX_SETP_FP<RegF32, "f32", f32imm, SETUEQ, SETOEQ, "eq">;
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defm SETPNEf32 : PTX_SETP_FP<RegF32, "f32", f32imm, SETUNE, SETONE, "ne">;
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defm SETPLTf32 : PTX_SETP_FP<RegF32, "f32", f32imm, SETULT, SETOLT, "lt">;
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defm SETPLEf32 : PTX_SETP_FP<RegF32, "f32", f32imm, SETULE, SETOLE, "le">;
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defm SETPGTf32 : PTX_SETP_FP<RegF32, "f32", f32imm, SETUGT, SETOGT, "gt">;
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defm SETPGEf32 : PTX_SETP_FP<RegF32, "f32", f32imm, SETUGE, SETOGE, "ge">;
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// Compare f64
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defm SETPEQf64 : PTX_SETP_FP<RegF64, "f64", SETUEQ, SETOEQ, "eq">;
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defm SETPNEf64 : PTX_SETP_FP<RegF64, "f64", SETUNE, SETONE, "ne">;
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defm SETPLTf64 : PTX_SETP_FP<RegF64, "f64", SETULT, SETOLT, "lt">;
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defm SETPLEf64 : PTX_SETP_FP<RegF64, "f64", SETULE, SETOLE, "le">;
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defm SETPGTf64 : PTX_SETP_FP<RegF64, "f64", SETUGT, SETOGT, "gt">;
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defm SETPGEf64 : PTX_SETP_FP<RegF64, "f64", SETUGE, SETOGE, "ge">;
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defm SETPEQf64 : PTX_SETP_FP<RegF64, "f64", f64imm, SETUEQ, SETOEQ, "eq">;
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defm SETPNEf64 : PTX_SETP_FP<RegF64, "f64", f64imm, SETUNE, SETONE, "ne">;
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defm SETPLTf64 : PTX_SETP_FP<RegF64, "f64", f64imm, SETULT, SETOLT, "lt">;
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defm SETPLEf64 : PTX_SETP_FP<RegF64, "f64", f64imm, SETULE, SETOLE, "le">;
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defm SETPGTf64 : PTX_SETP_FP<RegF64, "f64", f64imm, SETUGT, SETOGT, "gt">;
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defm SETPGEf64 : PTX_SETP_FP<RegF64, "f64", f64imm, SETUGE, SETOGE, "ge">;
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// .selp
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defm PTX_SELPu16 : PTX_SELP<RegI16, "u16">;
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defm PTX_SELPu32 : PTX_SELP<RegI32, "u32">;
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defm PTX_SELPu64 : PTX_SELP<RegI64, "u64">;
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defm PTX_SELPf32 : PTX_SELP<RegF32, "f32">;
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defm PTX_SELPf64 : PTX_SELP<RegF64, "f64">;
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defm SELPi16 : PTX_SELP<RegI16, "u16", i16imm, imm>;
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defm SELPi32 : PTX_SELP<RegI32, "u32", i32imm, imm>;
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defm SELPi64 : PTX_SELP<RegI64, "u64", i64imm, imm>;
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defm SELPf32 : PTX_SELP<RegF32, "f32", f32imm, fpimm>;
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defm SELPf64 : PTX_SELP<RegF64, "f64", f64imm, fpimm>;
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///===- Logic and Shift Instructions --------------------------------------===//
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@ -633,6 +651,24 @@ defm XOR : PTX_LOGIC<"xor", xor>;
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///===- Data Movement and Conversion Instructions -------------------------===//
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// any_extend
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// Implement the anyext instruction in terms of the PTX cvt instructions.
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//def : Pat<(i32 (anyext RegI16:$a)), (CVT_u32_u16 RegI16:$a)>;
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//def : Pat<(i64 (anyext RegI16:$a)), (CVT_u64_u16 RegI16:$a)>;
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//def : Pat<(i64 (anyext RegI32:$a)), (CVT_u64_u32 RegI32:$a)>;
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// bitconvert
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// These instructions implement the bit-wise conversion between integer and
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// floating-point types.
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def MOVi32f32
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: InstPTX<(outs RegI32:$d), (ins RegF32:$a), "mov.b32\t$d, $a", []>;
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def MOVf32i32
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: InstPTX<(outs RegF32:$d), (ins RegI32:$a), "mov.b32\t$d, $a", []>;
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def MOVi64f64
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: InstPTX<(outs RegI64:$d), (ins RegF64:$a), "mov.b64\t$d, $a", []>;
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def MOVf64i64
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: InstPTX<(outs RegF64:$d), (ins RegI64:$a), "mov.b64\t$d, $a", []>;
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let neverHasSideEffects = 1 in {
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def MOVPREDrr
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: InstPTX<(outs RegPred:$d), (ins RegPred:$a), "mov.pred\t$d, $a", []>;
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@ -678,213 +714,172 @@ let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
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[(set RegI64:$d, (PTXcopyaddress tglobaladdr:$a))]>;
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}
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// PTX cvt instructions
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// Note all of these may actually be used, we just define all possible patterns
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// here.
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// To i16
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def CVTu16u32
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: InstPTX<(outs RegI16:$d), (ins RegI32:$a), "cvt.u16.u32\t$d, $a", []>;
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def CVTu16u64
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: InstPTX<(outs RegI16:$d), (ins RegI64:$a), "cvt.u16.u64\t$d, $a", []>;
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def CVTu16f32
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: InstPTX<(outs RegI16:$d), (ins RegF32:$a), "cvt.rzi.u16.f32\t$d, $a", []>;
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def CVTs16f32
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: InstPTX<(outs RegI16:$d), (ins RegF32:$a), "cvt.rzi.s16.f32\t$d, $a", []>;
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def CVTu16f64
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: InstPTX<(outs RegI16:$d), (ins RegF64:$a), "cvt.rzi.u16.f64\t$d, $a", []>;
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def CVTs16f64
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: InstPTX<(outs RegI16:$d), (ins RegF64:$a), "cvt.rzi.s16.f64\t$d, $a", []>;
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// To i32
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def CVTu32u16
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: InstPTX<(outs RegI32:$d), (ins RegI16:$a), "cvt.u32.u16\t$d, $a", []>;
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def CVTs32s16
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: InstPTX<(outs RegI32:$d), (ins RegI16:$a), "cvt.s32.s16\t$d, $a", []>;
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def CVTu32u64
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: InstPTX<(outs RegI32:$d), (ins RegI64:$a), "cvt.u32.u64\t$d, $a", []>;
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def CVTu32f32
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: InstPTX<(outs RegI32:$d), (ins RegF32:$a), "cvt.rzi.u32.f32\t$d, $a", []>;
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def CVTs32f32
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: InstPTX<(outs RegI32:$d), (ins RegF32:$a), "cvt.rzi.s32.f32\t$d, $a", []>;
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def CVTu32f64
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: InstPTX<(outs RegI32:$d), (ins RegF64:$a), "cvt.rzi.u32.f64\t$d, $a", []>;
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def CVTs32f64
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: InstPTX<(outs RegI32:$d), (ins RegF64:$a), "cvt.rzi.s32.f64\t$d, $a", []>;
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// To i64
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def CVTu64u16
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: InstPTX<(outs RegI64:$d), (ins RegI16:$a), "cvt.u64.u16\t$d, $a", []>;
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def CVTs64s16
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: InstPTX<(outs RegI64:$d), (ins RegI16:$a), "cvt.s64.s16\t$d, $a", []>;
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def CVTu64u32
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: InstPTX<(outs RegI64:$d), (ins RegI32:$a), "cvt.u64.u32\t$d, $a", []>;
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def CVTs64s32
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: InstPTX<(outs RegI64:$d), (ins RegI32:$a), "cvt.s64.s32\t$d, $a", []>;
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def CVTu64f32
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: InstPTX<(outs RegI64:$d), (ins RegF32:$a), "cvt.rzi.u64.f32\t$d, $a", []>;
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def CVTs64f32
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: InstPTX<(outs RegI64:$d), (ins RegF32:$a), "cvt.rzi.s64.f32\t$d, $a", []>;
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def CVTu64f64
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: InstPTX<(outs RegI64:$d), (ins RegF64:$a), "cvt.rzi.u64.f64\t$d, $a", []>;
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def CVTs64f64
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: InstPTX<(outs RegI64:$d), (ins RegF64:$a), "cvt.rzi.s64.f64\t$d, $a", []>;
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// To f32
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def CVTf32u16
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: InstPTX<(outs RegF32:$d), (ins RegI16:$a), "cvt.rn.f32.u16\t$d, $a", []>;
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def CVTf32s16
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: InstPTX<(outs RegF32:$d), (ins RegI16:$a), "cvt.rn.f32.s16\t$d, $a", []>;
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def CVTf32u32
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: InstPTX<(outs RegF32:$d), (ins RegI32:$a), "cvt.rn.f32.u32\t$d, $a", []>;
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def CVTf32s32
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: InstPTX<(outs RegF32:$d), (ins RegI32:$a), "cvt.rn.f32.s32\t$d, $a", []>;
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def CVTf32u64
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: InstPTX<(outs RegF32:$d), (ins RegI64:$a), "cvt.rn.f32.u64\t$d, $a", []>;
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def CVTf32s64
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: InstPTX<(outs RegF32:$d), (ins RegI64:$a), "cvt.rn.f32.s64\t$d, $a", []>;
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def CVTf32f64
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: InstPTX<(outs RegF32:$d), (ins RegF64:$a), "cvt.rn.f32.f64\t$d, $a", []>;
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// To f64
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def CVTf64u16
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: InstPTX<(outs RegF64:$d), (ins RegI16:$a), "cvt.rn.f64.u16\t$d, $a", []>;
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def CVTf64s16
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: InstPTX<(outs RegF64:$d), (ins RegI16:$a), "cvt.rn.f64.s16\t$d, $a", []>;
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def CVTf64u32
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: InstPTX<(outs RegF64:$d), (ins RegI32:$a), "cvt.rn.f64.u32\t$d, $a", []>;
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def CVTf64s32
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: InstPTX<(outs RegF64:$d), (ins RegI32:$a), "cvt.rn.f64.s32\t$d, $a", []>;
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def CVTf64u64
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: InstPTX<(outs RegF64:$d), (ins RegI64:$a), "cvt.rn.f64.u64\t$d, $a", []>;
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def CVTf64s64
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: InstPTX<(outs RegF64:$d), (ins RegI64:$a), "cvt.rn.f64.s64\t$d, $a", []>;
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def CVTf64f32
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: InstPTX<(outs RegF64:$d), (ins RegF32:$a), "cvt.f64.f32\t$d, $a", []>;
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// Type conversion notes:
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// - PTX does not directly support converting a predicate to a value, so we
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// use a select instruction to select either 0 or 1 (integer or fp) based
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// on the truth value of the predicate.
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// - PTX does not directly support converting to a predicate type, so we fake it
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// by performing a greater-than test between the value and zero. This follows
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// the C convention that any non-zero value is equivalent to 'true'.
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// Conversion to pred
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// PTX does not directly support converting to a predicate type, so we fake it
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// by performing a greater-than test between the value and zero. This follows
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// the C convention that any non-zero value is equivalent to 'true'.
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def CVT_pred_u16
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: InstPTX<(outs RegPred:$d), (ins RegI16:$a), "setp.gt.u16\t$d, $a, 0",
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[(set RegPred:$d, (trunc RegI16:$a))]>;
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def CVT_pred_u32
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: InstPTX<(outs RegPred:$d), (ins RegI32:$a), "setp.gt.u32\t$d, $a, 0",
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[(set RegPred:$d, (trunc RegI32:$a))]>;
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def CVT_pred_u64
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: InstPTX<(outs RegPred:$d), (ins RegI64:$a), "setp.gt.u64\t$d, $a, 0",
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[(set RegPred:$d, (trunc RegI64:$a))]>;
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def CVT_pred_f32
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: InstPTX<(outs RegPred:$d), (ins RegF32:$a), "setp.gt.f32\t$d, $a, 0",
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[(set RegPred:$d, (fp_to_uint RegF32:$a))]>;
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def CVT_pred_f64
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: InstPTX<(outs RegPred:$d), (ins RegF64:$a), "setp.gt.f64\t$d, $a, 0",
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[(set RegPred:$d, (fp_to_uint RegF64:$a))]>;
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def : Pat<(i1 (trunc RegI16:$a)), (SETPGTu16ri RegI16:$a, 0)>;
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def : Pat<(i1 (trunc RegI32:$a)), (SETPGTu32ri RegI32:$a, 0)>;
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def : Pat<(i1 (trunc RegI64:$a)), (SETPGTu64ri RegI64:$a, 0)>;
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def : Pat<(i1 (fp_to_uint RegF32:$a)), (SETPGTu32ri (MOVi32f32 RegF32:$a), 0)>;
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def : Pat<(i1 (fp_to_uint RegF64:$a)), (SETPGTu64ri (MOVi64f64 RegF64:$a), 0)>;
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// Conversion to u16
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// PTX does not directly support converting a predicate to a value, so we
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// use a select instruction to select either 0 or 1 (integer or fp) based
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// on the truth value of the predicate.
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def CVT_u16_preda
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: InstPTX<(outs RegI16:$d), (ins RegPred:$a), "selp.u16\t$d, 1, 0, $a",
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[(set RegI16:$d, (anyext RegPred:$a))]>;
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def CVT_u16_pred
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: InstPTX<(outs RegI16:$d), (ins RegPred:$a), "selp.u16\t$d, 1, 0, $a",
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[(set RegI16:$d, (zext RegPred:$a))]>;
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def CVT_u16_preds
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: InstPTX<(outs RegI16:$d), (ins RegPred:$a), "selp.u16\t$d, 1, 0, $a",
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[(set RegI16:$d, (sext RegPred:$a))]>;
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def CVT_u16_u32
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: InstPTX<(outs RegI16:$d), (ins RegI32:$a), "cvt.u16.u32\t$d, $a",
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[(set RegI16:$d, (trunc RegI32:$a))]>;
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def CVT_u16_u64
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: InstPTX<(outs RegI16:$d), (ins RegI64:$a), "cvt.u16.u64\t$d, $a",
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[(set RegI16:$d, (trunc RegI64:$a))]>;
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def CVT_u16_f32
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: InstPTX<(outs RegI16:$d), (ins RegF32:$a), "cvt.rzi.u16.f32\t$d, $a",
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[(set RegI16:$d, (fp_to_uint RegF32:$a))]>;
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def CVT_u16_f64
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: InstPTX<(outs RegI16:$d), (ins RegF64:$a), "cvt.rzi.u16.f64\t$d, $a",
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[(set RegI16:$d, (fp_to_uint RegF64:$a))]>;
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def : Pat<(i16 (anyext RegPred:$a)), (SELPi16ii RegPred:$a, 1, 0)>;
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def : Pat<(i16 (sext RegPred:$a)), (SELPi16ii RegPred:$a, 0xFFFF, 0)>;
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def : Pat<(i16 (zext RegPred:$a)), (SELPi16ii RegPred:$a, 1, 0)>;
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def : Pat<(i16 (trunc RegI32:$a)), (CVTu16u32 RegI32:$a)>;
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def : Pat<(i16 (trunc RegI64:$a)), (CVTu16u64 RegI64:$a)>;
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def : Pat<(i16 (fp_to_uint RegF32:$a)), (CVTu16f32 RegF32:$a)>;
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def : Pat<(i16 (fp_to_sint RegF32:$a)), (CVTs16f32 RegF32:$a)>;
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def : Pat<(i16 (fp_to_uint RegF64:$a)), (CVTu16f64 RegF64:$a)>;
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def : Pat<(i16 (fp_to_sint RegF64:$a)), (CVTs16f64 RegF64:$a)>;
|
||||
|
||||
// Conversion to u32
|
||||
|
||||
def CVT_u32_pred
|
||||
: InstPTX<(outs RegI32:$d), (ins RegPred:$a), "selp.u32\t$d, 1, 0, $a",
|
||||
[(set RegI32:$d, (zext RegPred:$a))]>;
|
||||
|
||||
def CVT_u32_b16
|
||||
: InstPTX<(outs RegI32:$d), (ins RegI16:$a), "cvt.u32.u16\t$d, $a",
|
||||
[(set RegI32:$d, (anyext RegI16:$a))]>;
|
||||
|
||||
def CVT_u32_u16
|
||||
: InstPTX<(outs RegI32:$d), (ins RegI16:$a), "cvt.u32.u16\t$d, $a",
|
||||
[(set RegI32:$d, (zext RegI16:$a))]>;
|
||||
|
||||
def CVT_u32_preds
|
||||
: InstPTX<(outs RegI32:$d), (ins RegPred:$a), "selp.u32\t$d, 1, 0, $a",
|
||||
[(set RegI32:$d, (sext RegPred:$a))]>;
|
||||
|
||||
def CVT_u32_s16
|
||||
: InstPTX<(outs RegI32:$d), (ins RegI16:$a), "cvt.u32.s16\t$d, $a",
|
||||
[(set RegI32:$d, (sext RegI16:$a))]>;
|
||||
|
||||
def CVT_u32_u64
|
||||
: InstPTX<(outs RegI32:$d), (ins RegI64:$a), "cvt.u32.u64\t$d, $a",
|
||||
[(set RegI32:$d, (trunc RegI64:$a))]>;
|
||||
|
||||
def CVT_u32_f32
|
||||
: InstPTX<(outs RegI32:$d), (ins RegF32:$a), "cvt.rzi.u32.f32\t$d, $a",
|
||||
[(set RegI32:$d, (fp_to_uint RegF32:$a))]>;
|
||||
|
||||
def CVT_u32_f64
|
||||
: InstPTX<(outs RegI32:$d), (ins RegF64:$a), "cvt.rzi.u32.f64\t$d, $a",
|
||||
[(set RegI32:$d, (fp_to_uint RegF64:$a))]>;
|
||||
def : Pat<(i32 (anyext RegPred:$a)), (SELPi32ii RegPred:$a, 1, 0)>;
|
||||
def : Pat<(i32 (sext RegPred:$a)), (SELPi32ii RegPred:$a, 0xFFFFFFFF, 0)>;
|
||||
def : Pat<(i32 (zext RegPred:$a)), (SELPi32ii RegPred:$a, 1, 0)>;
|
||||
def : Pat<(i32 (anyext RegI16:$a)), (CVTu32u16 RegI16:$a)>;
|
||||
def : Pat<(i32 (sext RegI16:$a)), (CVTs32s16 RegI16:$a)>;
|
||||
def : Pat<(i32 (zext RegI16:$a)), (CVTu32u16 RegI16:$a)>;
|
||||
def : Pat<(i32 (trunc RegI64:$a)), (CVTu32u64 RegI64:$a)>;
|
||||
def : Pat<(i32 (fp_to_uint RegF32:$a)), (CVTu32f32 RegF32:$a)>;
|
||||
def : Pat<(i32 (fp_to_sint RegF32:$a)), (CVTs32f32 RegF32:$a)>;
|
||||
def : Pat<(i32 (fp_to_uint RegF64:$a)), (CVTu32f64 RegF64:$a)>;
|
||||
def : Pat<(i32 (fp_to_sint RegF64:$a)), (CVTs32f64 RegF64:$a)>;
|
||||
def : Pat<(i32 (bitconvert RegF32:$a)), (MOVi32f32 RegF32:$a)>;
|
||||
|
||||
// Conversion to u64
|
||||
|
||||
def CVT_u64_pred
|
||||
: InstPTX<(outs RegI64:$d), (ins RegPred:$a), "selp.u64\t$d, 1, 0, $a",
|
||||
[(set RegI64:$d, (zext RegPred:$a))]>;
|
||||
|
||||
def CVT_u64_preds
|
||||
: InstPTX<(outs RegI64:$d), (ins RegPred:$a), "selp.u64\t$d, 1, 0, $a",
|
||||
[(set RegI64:$d, (sext RegPred:$a))]>;
|
||||
|
||||
def CVT_u64_u16
|
||||
: InstPTX<(outs RegI64:$d), (ins RegI16:$a), "cvt.u64.u16\t$d, $a",
|
||||
[(set RegI64:$d, (zext RegI16:$a))]>;
|
||||
|
||||
def CVT_u64_s16
|
||||
: InstPTX<(outs RegI64:$d), (ins RegI16:$a), "cvt.u64.s16\t$d, $a",
|
||||
[(set RegI64:$d, (sext RegI16:$a))]>;
|
||||
|
||||
def CVT_u64_u32
|
||||
: InstPTX<(outs RegI64:$d), (ins RegI32:$a), "cvt.u64.u32\t$d, $a",
|
||||
[(set RegI64:$d, (zext RegI32:$a))]>;
|
||||
|
||||
def CVT_u64_s32
|
||||
: InstPTX<(outs RegI64:$d), (ins RegI32:$a), "cvt.u64.s32\t$d, $a",
|
||||
[(set RegI64:$d, (sext RegI32:$a))]>;
|
||||
|
||||
def CVT_u64_f32
|
||||
: InstPTX<(outs RegI64:$d), (ins RegF32:$a), "cvt.rzi.u64.f32\t$d, $a",
|
||||
[(set RegI64:$d, (fp_to_uint RegF32:$a))]>;
|
||||
|
||||
def CVT_u64_f64
|
||||
: InstPTX<(outs RegI64:$d), (ins RegF64:$a), "cvt.rzi.u64.f64\t$d, $a",
|
||||
[(set RegI64:$d, (fp_to_uint RegF64:$a))]>;
|
||||
def : Pat<(i64 (anyext RegPred:$a)), (SELPi64ii RegPred:$a, 1, 0)>;
|
||||
def : Pat<(i64 (sext RegPred:$a)), (SELPi64ii RegPred:$a,
|
||||
0xFFFFFFFFFFFFFFFF, 0)>;
|
||||
def : Pat<(i64 (zext RegPred:$a)), (SELPi64ii RegPred:$a, 1, 0)>;
|
||||
def : Pat<(i64 (anyext RegI16:$a)), (CVTu64u16 RegI16:$a)>;
|
||||
def : Pat<(i64 (sext RegI16:$a)), (CVTs64s16 RegI16:$a)>;
|
||||
def : Pat<(i64 (zext RegI16:$a)), (CVTu64u16 RegI16:$a)>;
|
||||
def : Pat<(i64 (anyext RegI32:$a)), (CVTu64u32 RegI32:$a)>;
|
||||
def : Pat<(i64 (sext RegI32:$a)), (CVTs64s32 RegI32:$a)>;
|
||||
def : Pat<(i64 (zext RegI32:$a)), (CVTu64u32 RegI32:$a)>;
|
||||
def : Pat<(i64 (fp_to_uint RegF32:$a)), (CVTu64f32 RegF32:$a)>;
|
||||
def : Pat<(i64 (fp_to_sint RegF32:$a)), (CVTs64f32 RegF32:$a)>;
|
||||
def : Pat<(i64 (fp_to_uint RegF64:$a)), (CVTu64f64 RegF64:$a)>;
|
||||
def : Pat<(i64 (fp_to_sint RegF64:$a)), (CVTs64f64 RegF64:$a)>;
|
||||
def : Pat<(i64 (bitconvert RegF64:$a)), (MOVi64f64 RegF64:$a)>;
|
||||
|
||||
// Conversion to f32
|
||||
|
||||
def CVT_f32_pred
|
||||
: InstPTX<(outs RegF32:$d), (ins RegPred:$a),
|
||||
"selp.f32\t$d, 0F3F800000, 0F00000000, $a", // 1.0
|
||||
[(set RegF32:$d, (uint_to_fp RegPred:$a))]>;
|
||||
|
||||
def CVT_f32_u16
|
||||
: InstPTX<(outs RegF32:$d), (ins RegI16:$a), "cvt.rn.f32.u16\t$d, $a",
|
||||
[(set RegF32:$d, (uint_to_fp RegI16:$a))]>;
|
||||
|
||||
def CVT_f32_u32
|
||||
: InstPTX<(outs RegF32:$d), (ins RegI32:$a), "cvt.rn.f32.u32\t$d, $a",
|
||||
[(set RegF32:$d, (uint_to_fp RegI32:$a))]>;
|
||||
|
||||
def CVT_f32_u64
|
||||
: InstPTX<(outs RegF32:$d), (ins RegI64:$a), "cvt.rn.f32.u64\t$d, $a",
|
||||
[(set RegF32:$d, (uint_to_fp RegI64:$a))]>;
|
||||
|
||||
def CVT_f32_f64
|
||||
: InstPTX<(outs RegF32:$d), (ins RegF64:$a), "cvt.rn.f32.f64\t$d, $a",
|
||||
[(set RegF32:$d, (fround RegF64:$a))]>;
|
||||
|
||||
def CVT_f32_s16
|
||||
: InstPTX<(outs RegF32:$d), (ins RegI16:$a), "cvt.rn.f32.s16\t$d, $a",
|
||||
[(set RegF32:$d, (sint_to_fp RegI16:$a))]>;
|
||||
|
||||
def CVT_f32_s32
|
||||
: InstPTX<(outs RegF32:$d), (ins RegI32:$a), "cvt.rn.f32.s32\t$d, $a",
|
||||
[(set RegF32:$d, (sint_to_fp RegI32:$a))]>;
|
||||
|
||||
def CVT_f32_s64
|
||||
: InstPTX<(outs RegF32:$d), (ins RegI64:$a), "cvt.rn.f32.s64\t$d, $a",
|
||||
[(set RegF32:$d, (sint_to_fp RegI64:$a))]>;
|
||||
|
||||
def : Pat<(f32 (uint_to_fp RegPred:$a)), (SELPf32rr RegPred:$a,
|
||||
(MOVf32i32 0x3F800000), (MOVf32i32 0))>;
|
||||
def : Pat<(f32 (uint_to_fp RegI16:$a)), (CVTf32u16 RegI16:$a)>;
|
||||
def : Pat<(f32 (sint_to_fp RegI16:$a)), (CVTf32s16 RegI16:$a)>;
|
||||
def : Pat<(f32 (uint_to_fp RegI32:$a)), (CVTf32u32 RegI32:$a)>;
|
||||
def : Pat<(f32 (sint_to_fp RegI32:$a)), (CVTf32s32 RegI32:$a)>;
|
||||
def : Pat<(f32 (uint_to_fp RegI64:$a)), (CVTf32u64 RegI64:$a)>;
|
||||
def : Pat<(f32 (sint_to_fp RegI64:$a)), (CVTf32s64 RegI64:$a)>;
|
||||
def : Pat<(f32 (fround RegF64:$a)), (CVTf32f64 RegF64:$a)>;
|
||||
def : Pat<(f32 (bitconvert RegI32:$a)), (MOVf32i32 RegI32:$a)>;
|
||||
|
||||
// Conversion to f64
|
||||
def : Pat<(f64 (uint_to_fp RegPred:$a)), (SELPf64rr RegPred:$a,
|
||||
(MOVf64i64 0x3F80000000000000), (MOVf64i64 0))>;
|
||||
def : Pat<(f64 (uint_to_fp RegI16:$a)), (CVTf64u16 RegI16:$a)>;
|
||||
def : Pat<(f64 (sint_to_fp RegI16:$a)), (CVTf64s16 RegI16:$a)>;
|
||||
def : Pat<(f64 (uint_to_fp RegI32:$a)), (CVTf64u32 RegI32:$a)>;
|
||||
def : Pat<(f64 (sint_to_fp RegI32:$a)), (CVTf64s32 RegI32:$a)>;
|
||||
def : Pat<(f64 (uint_to_fp RegI64:$a)), (CVTf64u64 RegI64:$a)>;
|
||||
def : Pat<(f64 (sint_to_fp RegI64:$a)), (CVTf64s64 RegI64:$a)>;
|
||||
def : Pat<(f64 (fextend RegF32:$a)), (CVTf64f32 RegF32:$a)>;
|
||||
def : Pat<(f64 (bitconvert RegI64:$a)), (MOVf64i64 RegI64:$a)>;
|
||||
|
||||
def CVT_f64_pred
|
||||
: InstPTX<(outs RegF64:$d), (ins RegPred:$a),
|
||||
"selp.f64\t$d, 0D3F80000000000000, 0D0000000000000000, $a", // 1.0
|
||||
[(set RegF64:$d, (uint_to_fp RegPred:$a))]>;
|
||||
|
||||
def CVT_f64_u16
|
||||
: InstPTX<(outs RegF64:$d), (ins RegI16:$a), "cvt.rn.f64.u16\t$d, $a",
|
||||
[(set RegF64:$d, (uint_to_fp RegI16:$a))]>;
|
||||
|
||||
def CVT_f64_u32
|
||||
: InstPTX<(outs RegF64:$d), (ins RegI32:$a), "cvt.rn.f64.u32\t$d, $a",
|
||||
[(set RegF64:$d, (uint_to_fp RegI32:$a))]>;
|
||||
|
||||
def CVT_f64_u64
|
||||
: InstPTX<(outs RegF64:$d), (ins RegI64:$a), "cvt.rn.f64.u64\t$d, $a",
|
||||
[(set RegF64:$d, (uint_to_fp RegI64:$a))]>;
|
||||
|
||||
def CVT_f64_f32
|
||||
: InstPTX<(outs RegF64:$d), (ins RegF32:$a), "cvt.f64.f32\t$d, $a",
|
||||
[(set RegF64:$d, (fextend RegF32:$a))]>;
|
||||
|
||||
def CVT_f64_s16
|
||||
: InstPTX<(outs RegF64:$d), (ins RegI16:$a), "cvt.rn.f64.s16\t$d, $a",
|
||||
[(set RegF64:$d, (sint_to_fp RegI16:$a))]>;
|
||||
|
||||
def CVT_f64_s32
|
||||
: InstPTX<(outs RegF64:$d), (ins RegI32:$a), "cvt.rn.f64.s32\t$d, $a",
|
||||
[(set RegF64:$d, (sint_to_fp RegI32:$a))]>;
|
||||
|
||||
def CVT_f64_s64
|
||||
: InstPTX<(outs RegF64:$d), (ins RegI64:$a), "cvt.rn.f64.s64\t$d, $a",
|
||||
[(set RegF64:$d, (sint_to_fp RegI64:$a))]>;
|
||||
|
||||
// NOTE: These are temporarily here to help test some Clang-generated code.
|
||||
// We really need to properly introduce anyext and bitconvert into the back-end.
|
||||
// ANY_EXTEND
|
||||
def ANY_EXTEND_I64_I32
|
||||
: InstPTX<(outs RegI64:$d), (ins RegI32:$a), "cvt.u64.u32\t$d, $a",
|
||||
[(set RegI64:$d, (anyext RegI32:$a))]>;
|
||||
|
||||
// BITCAST
|
||||
def BITCAST_I32_F32
|
||||
: InstPTX<(outs RegI32:$d), (ins RegF32:$a), "mov.b32\t$d, $a",
|
||||
[(set RegI32:$d, (bitconvert RegF32:$a))]>;
|
||||
|
||||
///===- Control Flow Instructions -----------------------------------------===//
|
||||
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
; RUN: llc < %s -march=ptx32 | FileCheck %s
|
||||
|
||||
; preds
|
||||
; preds
|
||||
; (note: we convert back to i32 to return)
|
||||
|
||||
define ptx_device i32 @cvt_pred_i16(i16 %x, i1 %y) {
|
||||
@ -37,7 +37,7 @@ define ptx_device i32 @cvt_pred_i64(i64 %x, i1 %y) {
|
||||
}
|
||||
|
||||
define ptx_device i32 @cvt_pred_f32(float %x, i1 %y) {
|
||||
; CHECK: setp.gt.f32 %p[[P0:[0-9]+]], %f{{[0-9]+}}, 0
|
||||
; CHECK: setp.gt.u32 %p[[P0:[0-9]+]], %r{{[0-9]+}}, 0
|
||||
; CHECK: and.pred %p2, %p[[P0:[0-9]+]], %p{{[0-9]+}};
|
||||
; CHECK: selp.u32 %ret{{[0-9]+}}, 1, 0, %p[[P0:[0-9]+]];
|
||||
; CHECK: ret;
|
||||
@ -48,7 +48,7 @@ define ptx_device i32 @cvt_pred_f32(float %x, i1 %y) {
|
||||
}
|
||||
|
||||
define ptx_device i32 @cvt_pred_f64(double %x, i1 %y) {
|
||||
; CHECK: setp.gt.f64 %p[[P0:[0-9]+]], %fd{{[0-9]+}}, 0
|
||||
; CHECK: setp.gt.u64 %p[[P0:[0-9]+]], %rd{{[0-9]+}}, 0
|
||||
; CHECK: and.pred %p2, %p[[P0:[0-9]+]], %p{{[0-9]+}};
|
||||
; CHECK: selp.u32 %ret{{[0-9]+}}, 1, 0, %p[[P0:[0-9]+]];
|
||||
; CHECK: ret;
|
||||
@ -172,7 +172,9 @@ define ptx_device i64 @cvt_i64_f64(double %x) {
|
||||
; f32
|
||||
|
||||
define ptx_device float @cvt_f32_preds(i1 %x) {
|
||||
; CHECK: selp.f32 %ret{{[0-9]+}}, 0F3F800000, 0F00000000, %p{{[0-9]+}};
|
||||
; CHECK: mov.b32 %f0, 1065353216;
|
||||
; CHECK: mov.b32 %f1, 0;
|
||||
; CHECK: selp.f32 %ret{{[0-9]+}}, %f0, %f1, %p{{[0-9]+}};
|
||||
; CHECK: ret;
|
||||
%a = uitofp i1 %x to float
|
||||
ret float %a
|
||||
@ -230,7 +232,9 @@ define ptx_device float @cvt_f32_s64(i64 %x) {
|
||||
; f64
|
||||
|
||||
define ptx_device double @cvt_f64_preds(i1 %x) {
|
||||
; CHECK: selp.f64 %ret{{[0-9]+}}, 0D3F80000000000000, 0D0000000000000000, %p{{[0-9]+}};
|
||||
; CHECK: mov.b64 %fd0, 4575657221408423936;
|
||||
; CHECK: mov.b64 %fd1, 0;
|
||||
; CHECK: selp.f64 %ret{{[0-9]+}}, %fd0, %fd1, %p{{[0-9]+}};
|
||||
; CHECK: ret;
|
||||
%a = uitofp i1 %x to double
|
||||
ret double %a
|
||||
|
||||
Loading…
Reference in New Issue
Block a user