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AMDGPU: Simplify debug printing

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247345 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault 2015-09-10 21:51:19 +00:00
parent 3a8d465ddd
commit d62d9ca7fa
3 changed files with 8 additions and 13 deletions
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15
lib/Target/AMDGPU/AMDILCFGStructurizer.cpp
View File

@ -1353,7 +1353,7 @@ int AMDGPUCFGStructurizer::improveSimpleJumpintoIf(MachineBasicBlock *HeadMBB,
// If MigrateTrue is true, then TrueBB is the block being "branched into"
// and if MigrateFalse is true, then FalseBB is the block being
// "branched into"
//
//
// Here is the pseudo code for how I think the optimization should work:
// 1. Insert MOV GPR0, 0 before the branch instruction in diamond_head.
// 2. Insert MOV GPR0, 1 before the branch instruction in branch_from.
@ -1372,7 +1372,7 @@ int AMDGPUCFGStructurizer::improveSimpleJumpintoIf(MachineBasicBlock *HeadMBB,
// the late machine optimization passes, however if we implement
// bool TargetRegisterInfo::requiresRegisterScavenging(
// const MachineFunction &MF)
// and have it return true, liveness will be tracked correctly
// and have it return true, liveness will be tracked correctly
// by generic optimization passes. We will also need to make sure that
// all of our target-specific passes that run after regalloc and before
// the CFGStructurizer track liveness and we will need to modify this pass
@ -1695,10 +1695,7 @@ void AMDGPUCFGStructurizer::migrateInstruction(MachineBasicBlock *SrcMBB,
);
SpliceEnd = SrcMBB->end();
} else {
DEBUG(
dbgs() << "migrateInstruction see branch instr\n" ;
BranchMI->dump();
);
DEBUG(dbgs() << "migrateInstruction see branch instr: " << *BranchMI);
SpliceEnd = BranchMI;
}
DEBUG(
@ -1711,7 +1708,7 @@ void AMDGPUCFGStructurizer::migrateInstruction(MachineBasicBlock *SrcMBB,
DEBUG(
dbgs() << "migrateInstruction after splice dstSize = " << DstMBB->size()
<< "srcSize = " << SrcMBB->size() << "\n";
<< "srcSize = " << SrcMBB->size() << '\n';
);
}
@ -1743,7 +1740,7 @@ void AMDGPUCFGStructurizer::removeUnconditionalBranch(MachineBasicBlock *MBB) {
// test_fc_do_while_or.c need to fix the upstream on this to remove the loop.
while ((BranchMI = getLoopendBlockBranchInstr(MBB))
&& isUncondBranch(BranchMI)) {
DEBUG(dbgs() << "Removing uncond branch instr"; BranchMI->dump(););
DEBUG(dbgs() << "Removing uncond branch instr: " << *BranchMI);
BranchMI->eraseFromParent();
}
}
@ -1759,7 +1756,7 @@ void AMDGPUCFGStructurizer::removeRedundantConditionalBranch(
MachineInstr *BranchMI = getNormalBlockBranchInstr(MBB);
assert(BranchMI && isCondBranch(BranchMI));
DEBUG(dbgs() << "Removing unneeded cond branch instr"; BranchMI->dump(););
DEBUG(dbgs() << "Removing unneeded cond branch instr: " << *BranchMI);
BranchMI->eraseFromParent();
SHOWNEWBLK(MBB1, "Removing redundant successor");
MBB->removeSuccessor(MBB1);

4
lib/Target/AMDGPU/SIFixSGPRCopies.cpp
View File

@ -215,10 +215,8 @@ bool SIFixSGPRCopies::runOnMachineFunction(MachineFunction &MF) {
I != E; ++I) {
MachineInstr &MI = *I;
if (MI.getOpcode() == AMDGPU::COPY && isVGPRToSGPRCopy(MI, TRI, MRI)) {
DEBUG(dbgs() << "Fixing VGPR -> SGPR copy:\n");
DEBUG(MI.print(dbgs()));
DEBUG(dbgs() << "Fixing VGPR -> SGPR copy: " << MI);
TII->moveToVALU(MI);
}
switch (MI.getOpcode()) {

2
lib/Target/AMDGPU/SIShrinkInstructions.cpp
View File

@ -283,7 +283,7 @@ bool SIShrinkInstructions::runOnMachineFunction(MachineFunction &MF) {
}
// We can shrink this instruction
DEBUG(dbgs() << "Shrinking "; MI.dump(); dbgs() << '\n';);
DEBUG(dbgs() << "Shrinking " << MI);
MachineInstrBuilder Inst32 =
BuildMI(MBB, I, MI.getDebugLoc(), TII->get(Op32));