From d64f8eb85d722ec77f5036d348b7f5ce828e78cd Mon Sep 17 00:00:00 2001 From: Hiroshi Inoue Date: Sat, 24 Jun 2017 16:00:26 +0000 Subject: [PATCH] fix trivial typos in comment, NFC git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306211 cdac9f57-aa62-4fd3-8940-286f4534e8a0 --- lib/Analysis/TypeBasedAliasAnalysis.cpp | 2 +- lib/Target/AArch64/AArch64SchedA57.td | 2 +- test/CodeGen/AArch64/arm64-shrink-v1i64.ll | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/lib/Analysis/TypeBasedAliasAnalysis.cpp b/lib/Analysis/TypeBasedAliasAnalysis.cpp index e920c4c4e6b..cd9972ab56a 100644 --- a/lib/Analysis/TypeBasedAliasAnalysis.cpp +++ b/lib/Analysis/TypeBasedAliasAnalysis.cpp @@ -58,7 +58,7 @@ // // The struct type node has a name and a list of pairs, one pair for each member // of the struct. The first element of each pair is a type node (a struct type -// node or a sclar type node), specifying the type of the member, the second +// node or a scalar type node), specifying the type of the member, the second // element of each pair is the offset of the member. // // Given an example diff --git a/lib/Target/AArch64/AArch64SchedA57.td b/lib/Target/AArch64/AArch64SchedA57.td index 303398ea0b7..5d1608ef04a 100644 --- a/lib/Target/AArch64/AArch64SchedA57.td +++ b/lib/Target/AArch64/AArch64SchedA57.td @@ -13,7 +13,7 @@ //===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===// -// The Cortex-A57 is a traditional superscaler microprocessor with a +// The Cortex-A57 is a traditional superscalar microprocessor with a // conservative 3-wide in-order stage for decode and dispatch. Combined with the // much wider out-of-order issue stage, this produced a need to carefully // schedule micro-ops so that all three decoded each cycle are successfully diff --git a/test/CodeGen/AArch64/arm64-shrink-v1i64.ll b/test/CodeGen/AArch64/arm64-shrink-v1i64.ll index 3e926d42740..57cc8120b91 100644 --- a/test/CodeGen/AArch64/arm64-shrink-v1i64.ll +++ b/test/CodeGen/AArch64/arm64-shrink-v1i64.ll @@ -3,7 +3,7 @@ ; The DAGCombiner tries to do following shrink: ; Convert x+y to (VT)((SmallVT)x+(SmallVT)y) ; But currently it can't handle vector type and will trigger an assertion failure -; when it tries to generate an add mixed using vector type and scaler type. +; when it tries to generate an add mixed using vector type and scalar type. ; This test checks that such assertion failur should not happen. define <1 x i64> @dotest(<1 x i64> %in0) { entry: