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TableGen: use PrintMethods to print more aliases

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208607 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tim Northover 2014-05-12 18:04:06 +00:00
parent 2161fd6114
commit d6cd0381f6
38 changed files with 463 additions and 308 deletions
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7
lib/Target/AArch64/AArch64InstrInfo.td
View File

@ -1587,6 +1587,7 @@ def inv_cond_code_op_asmoperand : AsmOperandClass {
def inv_cond_code_op : Operand<i32> {
let ParserMatchClass = inv_cond_code_op_asmoperand;
let PrintMethod = "printInverseCondCodeOperand";
}
// Having a separate operand for the selectable use-case is debatable, but gives
@ -3864,15 +3865,15 @@ let Defs = [NZCV] in {
Sched<[WriteALU, ReadALU]>;
}
def : InstAlias<"tst $Rn, $Imm",
(ANDSwwi WZR, GPR32:$Rn, logical_imm32_operand:$Imm)>;
def : InstAlias<"tst $Rn, $Imm",
(ANDSxxi XZR, GPR64:$Rn, logical_imm64_operand:$Imm)>;
// FIXME: these sometimes are canonical.
def : InstAlias<"mov $Rd, $Imm",
(ORRwwi GPR32wsp:$Rd, WZR, logical_imm32_mov_operand:$Imm)>;
(ORRwwi GPR32wsp:$Rd, WZR, logical_imm32_mov_operand:$Imm), 0>;
def : InstAlias<"mov $Rd, $Imm",
(ORRxxi GPR64xsp:$Rd, XZR, logical_imm64_mov_operand:$Imm)>;
(ORRxxi GPR64xsp:$Rd, XZR, logical_imm64_mov_operand:$Imm), 0>;
//===----------------------------------------------------------------------===//
// Logical (shifted register) instructions

9
lib/Target/AArch64/InstPrinter/AArch64InstPrinter.cpp
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@ -210,6 +210,15 @@ AArch64InstPrinter::printCondCodeOperand(const MCInst *MI, unsigned OpNum,
O << A64CondCodeToString(static_cast<A64CC::CondCodes>(MO.getImm()));
}
void
AArch64InstPrinter::printInverseCondCodeOperand(const MCInst *MI,
unsigned OpNum,
raw_ostream &O) {
A64CC::CondCodes CC =
static_cast<A64CC::CondCodes>(MI->getOperand(OpNum).getImm());
O << A64CondCodeToString(A64InvertCondCode(CC));
}
template <unsigned field_width, unsigned scale> void
AArch64InstPrinter::printLabelOperand(const MCInst *MI, unsigned OpNum,
raw_ostream &O) {

4
lib/Target/AArch64/InstPrinter/AArch64InstPrinter.h
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@ -31,6 +31,8 @@ public:
// Autogenerated by tblgen
void printInstruction(const MCInst *MI, raw_ostream &O);
bool printAliasInstr(const MCInst *MI, raw_ostream &O);
void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
unsigned PrintMethodIdx, raw_ostream &O);
static const char *getRegisterName(unsigned RegNo);
static const char *getInstructionName(unsigned Opcode);
@ -62,6 +64,8 @@ public:
void printCondCodeOperand(const MCInst *MI, unsigned OpNum,
raw_ostream &O);
void printInverseCondCodeOperand(const MCInst *MI, unsigned OpNum,
raw_ostream &O);
void printCRxOperand(const MCInst *MI, unsigned OpNum,
raw_ostream &O);

16
lib/Target/ARM64/ARM64InstrFormats.td
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@ -1904,6 +1904,10 @@ def ccode : Operand<i32> {
let PrintMethod = "printCondCode";
}
def inv_ccode : Operand<i32> {
let PrintMethod = "printInverseCondCode";
}
let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
class BaseCondSetFlagsImm<bit op, RegisterClass regtype, string asm>
: I<(outs), (ins regtype:$Rn, imm0_31:$imm, imm0_15:$nzcv, ccode:$cond),
@ -5571,11 +5575,13 @@ class SIMDUMov<bit Q, string size, ValueType vectype, RegisterClass regtype,
: BaseSIMDMov<Q, size, 0b0111, regtype, idxtype, "umov",
[(set regtype:$Rd, (vector_extract (vectype V128:$Rn), idxtype:$idx))]>;
// FIXME: these aliases should be canonical, but TableGen can't handle the
// alternate syntaxes.
class SIMDMovAlias<string asm, string size, Instruction inst,
RegisterClass regtype, Operand idxtype>
: InstAlias<asm#"{\t$dst, $src"#size#"$idx" #
"|" # size # "\t$dst, $src$idx}",
(inst regtype:$dst, V128:$src, idxtype:$idx)>;
(inst regtype:$dst, V128:$src, idxtype:$idx), 0>;
multiclass SMov {
def vi8to32 : SIMDSMov<0, ".b", GPR32, VectorIndexB> {
@ -5659,16 +5665,18 @@ class SIMDInsFromElement<string size, ValueType vectype,
(elttype (vector_extract (vectype V128:$Rn), idxtype:$idx2)),
idxtype:$idx))]>;
// FIXME: the MOVs should be canonical, but TableGen's alias printing can't cope
// with syntax variants.
class SIMDInsMainMovAlias<string size, Instruction inst,
RegisterClass regtype, Operand idxtype>
: InstAlias<"mov" # "{\t$dst" # size # "$idx, $src" #
"|" # size #"\t$dst$idx, $src}",
(inst V128:$dst, idxtype:$idx, regtype:$src)>;
(inst V128:$dst, idxtype:$idx, regtype:$src), 0>;
class SIMDInsElementMovAlias<string size, Instruction inst,
Operand idxtype>
: InstAlias<"mov" # "{\t$dst" # size # "$idx, $src" # size # "$idx2" #
# "|" # size #" $dst$idx, $src$idx2}",
(inst V128:$dst, idxtype:$idx, V128:$src, idxtype:$idx2)>;
(inst V128:$dst, idxtype:$idx, V128:$src, idxtype:$idx2), 0>;
multiclass SIMDIns {
@ -5909,7 +5917,7 @@ class SIMDScalarCPYAlias<string asm, string size, Instruction inst,
RegisterClass regtype, RegisterOperand vectype, Operand idxtype>
: InstAlias<asm # "{\t$dst, $src" # size # "$index" #
# "|\t$dst, $src$index}",
(inst regtype:$dst, vectype:$src, idxtype:$index)>;
(inst regtype:$dst, vectype:$src, idxtype:$index), 0>;
multiclass SIMDScalarCPY<string asm> {

54
lib/Target/ARM64/ARM64InstrInfo.td
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@ -554,6 +554,8 @@ def : Pat<(sub GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
(ADDXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
}
// FIXME: TableGen can very nearly handle printing all of these, we should make
// it work properly.
def : InstAlias<"neg $dst, $src", (SUBWrs GPR32:$dst, WZR, GPR32:$src, 0)>;
def : InstAlias<"neg $dst, $src", (SUBXrs GPR64:$dst, XZR, GPR64:$src, 0)>;
def : InstAlias<"neg $dst, $src, $shift",
@ -673,10 +675,13 @@ defm AND : LogicalImm<0b00, "and", and>;
defm EOR : LogicalImm<0b10, "eor", xor>;
defm ORR : LogicalImm<0b01, "orr", or>;
// FIXME: these aliases *are* canonical sometimes (when movz can't be
// used). Actually, it seems to be working right now, but putting logical_immXX
// here is a bit dodgy on the AsmParser side too.
def : InstAlias<"mov $dst, $imm", (ORRWri GPR32sp:$dst, WZR,
logical_imm32:$imm)>;
logical_imm32:$imm), 0>;
def : InstAlias<"mov $dst, $imm", (ORRXri GPR64sp:$dst, XZR,
logical_imm64:$imm)>;
logical_imm64:$imm), 0>;
// (register)
@ -922,27 +927,30 @@ def : Pat<(ARM64csel (i64 0), (i64 -1), (i32 imm:$cc), NZCV),
// The inverse of the condition code from the alias instruction is what is used
// in the aliased instruction. The parser all ready inverts the condition code
// for these aliases.
// FIXME: Is this the correct way to handle these aliases?
def : InstAlias<"cset $dst, $cc", (CSINCWr GPR32:$dst, WZR, WZR, ccode:$cc)>;
def : InstAlias<"cset $dst, $cc", (CSINCXr GPR64:$dst, XZR, XZR, ccode:$cc)>;
def : InstAlias<"cset $dst, $cc",
(CSINCWr GPR32:$dst, WZR, WZR, inv_ccode:$cc)>;
def : InstAlias<"cset $dst, $cc",
(CSINCXr GPR64:$dst, XZR, XZR, inv_ccode:$cc)>;
def : InstAlias<"csetm $dst, $cc", (CSINVWr GPR32:$dst, WZR, WZR, ccode:$cc)>;
def : InstAlias<"csetm $dst, $cc", (CSINVXr GPR64:$dst, XZR, XZR, ccode:$cc)>;
def : InstAlias<"csetm $dst, $cc",
(CSINVWr GPR32:$dst, WZR, WZR, inv_ccode:$cc)>;
def : InstAlias<"csetm $dst, $cc",
(CSINVXr GPR64:$dst, XZR, XZR, inv_ccode:$cc)>;
def : InstAlias<"cinc $dst, $src, $cc",
(CSINCWr GPR32:$dst, GPR32:$src, GPR32:$src, ccode:$cc)>;
(CSINCWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>;
def : InstAlias<"cinc $dst, $src, $cc",
(CSINCXr GPR64:$dst, GPR64:$src, GPR64:$src, ccode:$cc)>;
(CSINCXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;
def : InstAlias<"cinv $dst, $src, $cc",
(CSINVWr GPR32:$dst, GPR32:$src, GPR32:$src, ccode:$cc)>;
(CSINVWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>;
def : InstAlias<"cinv $dst, $src, $cc",
(CSINVXr GPR64:$dst, GPR64:$src, GPR64:$src, ccode:$cc)>;
(CSINVXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;
def : InstAlias<"cneg $dst, $src, $cc",
(CSNEGWr GPR32:$dst, GPR32:$src, GPR32:$src, ccode:$cc)>;
(CSNEGWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>;
def : InstAlias<"cneg $dst, $src, $cc",
(CSNEGXr GPR64:$dst, GPR64:$src, GPR64:$src, ccode:$cc)>;
(CSNEGXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;
//===----------------------------------------------------------------------===//
// PC-relative instructions.
@ -3728,10 +3736,12 @@ def : Pat<(v4f32 (ARM64dup (f32 fpimm0))), (MOVIv2d_ns (i32 0))>;
// EDIT per word & halfword: 2s, 4h, 4s, & 8h
defm MOVI : SIMDModifiedImmVectorShift<0, 0b10, 0b00, "movi">;
def : InstAlias<"movi $Vd.4h, $imm", (MOVIv4i16 V64:$Vd, imm0_255:$imm, 0)>;
def : InstAlias<"movi $Vd.8h, $imm", (MOVIv8i16 V128:$Vd, imm0_255:$imm, 0)>;
def : InstAlias<"movi $Vd.2s, $imm", (MOVIv2i32 V64:$Vd, imm0_255:$imm, 0)>;
def : InstAlias<"movi $Vd.4s, $imm", (MOVIv4i32 V128:$Vd, imm0_255:$imm, 0)>;
// FIXME: these should be canonical but the TableGen alias printer can't cope
// with syntax variants.
def : InstAlias<"movi $Vd.4h, $imm", (MOVIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
def : InstAlias<"movi $Vd.8h, $imm", (MOVIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
def : InstAlias<"movi $Vd.2s, $imm", (MOVIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
def : InstAlias<"movi $Vd.4s, $imm", (MOVIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
def : InstAlias<"movi.4h $Vd, $imm", (MOVIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
def : InstAlias<"movi.8h $Vd, $imm", (MOVIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
@ -3768,10 +3778,12 @@ def MOVIv16b_ns : SIMDModifiedImmVectorNoShift<1, 0, 0b1110, V128, imm0_255,
// EDIT per word & halfword: 2s, 4h, 4s, & 8h
defm MVNI : SIMDModifiedImmVectorShift<1, 0b10, 0b00, "mvni">;
def : InstAlias<"mvni $Vd.4h, $imm", (MVNIv4i16 V64:$Vd, imm0_255:$imm, 0)>;
def : InstAlias<"mvni $Vd.8h, $imm", (MVNIv8i16 V128:$Vd, imm0_255:$imm, 0)>;
def : InstAlias<"mvni $Vd.2s, $imm", (MVNIv2i32 V64:$Vd, imm0_255:$imm, 0)>;
def : InstAlias<"mvni $Vd.4s, $imm", (MVNIv4i32 V128:$Vd, imm0_255:$imm, 0)>;
// FIXME: these should be canonical, but TableGen can't do aliases & syntax
// variants together.
def : InstAlias<"mvni $Vd.4h, $imm", (MVNIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
def : InstAlias<"mvni $Vd.8h, $imm", (MVNIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
def : InstAlias<"mvni $Vd.2s, $imm", (MVNIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
def : InstAlias<"mvni $Vd.4s, $imm", (MVNIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
def : InstAlias<"mvni.4h $Vd, $imm", (MVNIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
def : InstAlias<"mvni.8h $Vd, $imm", (MVNIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;

4
lib/Target/ARM64/ARM64RegisterInfo.td
View File

@ -170,6 +170,10 @@ def tcGPR64 : RegisterClass<"ARM64", [i64], 64, (sub GPR64common, X19, X20, X21,
// GPR register classes for post increment amount of vector load/store that
// has alternate printing when Rm=31 and prints a constant immediate value
// equal to the total number of bytes transferred.
// FIXME: TableGen *should* be able to do these itself now. There appears to be
// a bug in counting how many operands a Post-indexed MCInst should have which
// means the aliases don't trigger.
def GPR64pi1 : RegisterOperand<GPR64, "printPostIncOperand<1>">;
def GPR64pi2 : RegisterOperand<GPR64, "printPostIncOperand<2>">;
def GPR64pi3 : RegisterOperand<GPR64, "printPostIncOperand<3>">;

20
lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp
View File

@ -221,18 +221,8 @@ void ARM64InstPrinter::printInst(const MCInst *MI, raw_ostream &O,
return;
}
// ANDS WZR, Wn, #imm ==> TST Wn, #imm
// ANDS XZR, Xn, #imm ==> TST Xn, #imm
if (Opcode == ARM64::ANDSWri && MI->getOperand(0).getReg() == ARM64::WZR) {
O << "\ttst\t" << getRegisterName(MI->getOperand(1).getReg()) << ", ";
printLogicalImm32(MI, 2, O);
return;
}
if (Opcode == ARM64::ANDSXri && MI->getOperand(0).getReg() == ARM64::XZR) {
O << "\ttst\t" << getRegisterName(MI->getOperand(1).getReg()) << ", ";
printLogicalImm64(MI, 2, O);
return;
}
// FIXME: TableGen should be able to do all of these now.
// ANDS WZR, Wn, Wm{, lshift #imm} ==> TST Wn{, lshift #imm}
// ANDS XZR, Xn, Xm{, lshift #imm} ==> TST Xn{, lshift #imm}
if ((Opcode == ARM64::ANDSWrs && MI->getOperand(0).getReg() == ARM64::WZR) ||
@ -1166,6 +1156,12 @@ void ARM64InstPrinter::printCondCode(const MCInst *MI, unsigned OpNum,
O << ARM64CC::getCondCodeName(CC);
}
void ARM64InstPrinter::printInverseCondCode(const MCInst *MI, unsigned OpNum,
raw_ostream &O) {
ARM64CC::CondCode CC = (ARM64CC::CondCode)MI->getOperand(OpNum).getImm();
O << ARM64CC::getCondCodeName(ARM64CC::getInvertedCondCode(CC));
}
void ARM64InstPrinter::printAMNoIndex(const MCInst *MI, unsigned OpNum,
raw_ostream &O) {
O << '[' << getRegisterName(MI->getOperand(OpNum).getReg()) << ']';

5
lib/Target/ARM64/InstPrinter/ARM64InstPrinter.h
View File

@ -34,6 +34,8 @@ public:
// Autogenerated by tblgen.
virtual void printInstruction(const MCInst *MI, raw_ostream &O);
virtual bool printAliasInstr(const MCInst *MI, raw_ostream &O);
virtual void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
unsigned PrintMethodIdx, raw_ostream &O);
virtual StringRef getRegName(unsigned RegNo) const {
return getRegisterName(RegNo);
}
@ -62,6 +64,7 @@ protected:
void printExtendedRegister(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printExtend(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printCondCode(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printInverseCondCode(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printDotCondCode(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printAlignedLabel(const MCInst *MI, unsigned OpNum, raw_ostream &O);
void printAMIndexed(const MCInst *MI, unsigned OpNum, unsigned Scale,
@ -132,6 +135,8 @@ public:
void printInstruction(const MCInst *MI, raw_ostream &O) override;
bool printAliasInstr(const MCInst *MI, raw_ostream &O) override;
virtual void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
unsigned PrintMethodIdx, raw_ostream &O);
StringRef getRegName(unsigned RegNo) const override {
return getRegisterName(RegNo);
}

2
lib/Target/Mips/InstPrinter/MipsInstPrinter.h
View File

@ -89,6 +89,8 @@ public:
void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot) override;
bool printAliasInstr(const MCInst *MI, raw_ostream &OS);
void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
unsigned PrintMethodIdx, raw_ostream &O);
private:
void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);

2
lib/Target/Mips/MipsInstrInfo.td
View File

@ -1284,8 +1284,8 @@ def : MipsInstAlias<"beqz $rs,$offset",
(BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
def : MipsInstAlias<"syscall", (SYSCALL 0), 1>;
def : MipsInstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
def : MipsInstAlias<"break", (BREAK 0, 0), 1>;
def : MipsInstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
def : MipsInstAlias<"ei", (EI ZERO), 1>;
def : MipsInstAlias<"di", (DI ZERO), 1>;

2
lib/Target/Sparc/InstPrinter/SparcInstPrinter.h
View File

@ -38,6 +38,8 @@ public:
// Autogenerated by tblgen.
void printInstruction(const MCInst *MI, raw_ostream &O);
bool printAliasInstr(const MCInst *MI, raw_ostream &O);
void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
unsigned PrintMethodIdx, raw_ostream &O);
static const char *getRegisterName(unsigned RegNo);
void printOperand(const MCInst *MI, int opNum, raw_ostream &OS);

2
lib/Target/X86/InstPrinter/X86ATTInstPrinter.h
View File

@ -32,6 +32,8 @@ public:
// Autogenerated by tblgen, returns true if we successfully printed an
// alias.
bool printAliasInstr(const MCInst *MI, raw_ostream &OS);
void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
unsigned PrintMethodIdx, raw_ostream &O);
// Autogenerated by tblgen.
void printInstruction(const MCInst *MI, raw_ostream &OS);

28
test/CodeGen/AArch64/addsub-shifted.ll
View File

@ -1,5 +1,5 @@
; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
; RUN: llc -verify-machineinstrs %s -o - -mtriple=arm64-apple-ios7.0 | FileCheck %s
; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-AARCH64
; RUN: llc -verify-machineinstrs %s -o - -mtriple=arm64-apple-ios7.0 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-ARM64
@var32 = global i32 0
@var64 = global i64 0
@ -36,7 +36,8 @@ define void @test_lsl_arith(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) {
%shift4a = shl i32 %lhs4a, 15
%val4a = sub i32 0, %shift4a
store volatile i32 %val4a, i32* @var32
; CHECK: sub {{w[0-9]+}}, wzr, {{w[0-9]+}}, lsl #15
; CHECK-AARCH64: neg {{w[0-9]+}}, {{w[0-9]+}}, lsl #15
; CHECK-ARM64: sub {{w[0-9]+}}, wzr, {{w[0-9]+}}, lsl #15
%rhs5 = load volatile i64* @var64
%shift5 = shl i64 %rhs5, 18
@ -67,7 +68,8 @@ define void @test_lsl_arith(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) {
%shift8a = shl i64 %lhs8a, 60
%val8a = sub i64 0, %shift8a
store volatile i64 %val8a, i64* @var64
; CHECK: sub {{x[0-9]+}}, xzr, {{x[0-9]+}}, lsl #60
; CHECK-AARCH64: neg {{x[0-9]+}}, {{x[0-9]+}}, lsl #60
; CHECK-ARM64: sub {{x[0-9]+}}, xzr, {{x[0-9]+}}, lsl #60
ret void
; CHECK: ret
@ -100,7 +102,8 @@ define void @test_lsr_arith(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) {
%shift4a = lshr i32 %lhs32, 15
%val4a = sub i32 0, %shift4a
store volatile i32 %val4a, i32* @var32
; CHECK: sub {{w[0-9]+}}, wzr, {{w[0-9]+}}, lsr #15
; CHECK-AARCH64: neg {{w[0-9]+}}, {{w[0-9]+}}, lsr #15
; CHECK-ARM64: sub {{w[0-9]+}}, wzr, {{w[0-9]+}}, lsr #15
%shift5 = lshr i64 %rhs64, 18
%val5 = add i64 %lhs64, %shift5
@ -126,7 +129,8 @@ define void @test_lsr_arith(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) {
%shift8a = lshr i64 %lhs64, 45
%val8a = sub i64 0, %shift8a
store volatile i64 %val8a, i64* @var64
; CHECK: sub {{x[0-9]+}}, xzr, {{x[0-9]+}}, lsr #45
; CHECK-AARCH64: neg {{x[0-9]+}}, {{x[0-9]+}}, lsr #45
; CHECK-ARM64: sub {{x[0-9]+}}, xzr, {{x[0-9]+}}, lsr #45
ret void
; CHECK: ret
@ -159,7 +163,8 @@ define void @test_asr_arith(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) {
%shift4a = ashr i32 %lhs32, 15
%val4a = sub i32 0, %shift4a
store volatile i32 %val4a, i32* @var32
; CHECK: sub {{w[0-9]+}}, wzr, {{w[0-9]+}}, asr #15
; CHECK-AARCH64: neg {{w[0-9]+}}, {{w[0-9]+}}, asr #15
; CHECK-ARM64: sub {{w[0-9]+}}, wzr, {{w[0-9]+}}, asr #15
%shift5 = ashr i64 %rhs64, 18
%val5 = add i64 %lhs64, %shift5
@ -185,7 +190,8 @@ define void @test_asr_arith(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) {
%shift8a = ashr i64 %lhs64, 45
%val8a = sub i64 0, %shift8a
store volatile i64 %val8a, i64* @var64
; CHECK: sub {{x[0-9]+}}, xzr, {{x[0-9]+}}, asr #45
; CHECK-AARCH64: neg {{x[0-9]+}}, {{x[0-9]+}}, asr #45
; CHECK-ARM64: sub {{x[0-9]+}}, xzr, {{x[0-9]+}}, asr #45
ret void
; CHECK: ret
@ -246,7 +252,8 @@ define i32 @test_cmn(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) {
br i1 %tst1, label %t2, label %end
; Important that this isn't lowered to a cmn instruction because if %rhs32 ==
; 0 then the results will differ.
; CHECK: sub [[RHS:w[0-9]+]], wzr, {{w[0-9]+}}, lsl #13
; CHECK-AARCH64: neg [[RHS:w[0-9]+]], {{w[0-9]+}}, lsl #13
; CHECK-ARM64: sub [[RHS:w[0-9]+]], wzr, {{w[0-9]+}}, lsl #13
; CHECK: cmp {{w[0-9]+}}, [[RHS]]
t2:
@ -269,7 +276,8 @@ t4:
%tst4 = icmp slt i64 %lhs64, %val4
br i1 %tst4, label %t5, label %end
; Again, it's important that cmn isn't used here in case %rhs64 == 0.
; CHECK: sub [[RHS:x[0-9]+]], xzr, {{x[0-9]+}}, lsl #43
; CHECK-AARCH64: neg [[RHS:x[0-9]+]], {{x[0-9]+}}, lsl #43
; CHECK-ARM64: sub [[RHS:x[0-9]+]], xzr, {{x[0-9]+}}, lsl #43
; CHECK: cmp {{x[0-9]+}}, [[RHS]]
t5:

8
test/CodeGen/AArch64/cond-sel.ll
View File

@ -187,13 +187,13 @@ define void @test_cset(i32 %lhs, i32 %rhs, i64 %lhs64) {
%val1 = zext i1 %tst1 to i32
store i32 %val1, i32* @var32
; CHECK: cmp {{w[0-9]+}}, {{w[0-9]+}}
; CHECK: csinc {{w[0-9]+}}, wzr, wzr, ne
; CHECK: cset {{w[0-9]+}}, eq
%rhs64 = sext i32 %rhs to i64
%tst2 = icmp ule i64 %lhs64, %rhs64
%val2 = zext i1 %tst2 to i64
store i64 %val2, i64* @var64
; CHECK: csinc {{w[0-9]+}}, wzr, wzr, hi
; CHECK: cset {{w[0-9]+}}, ls
ret void
; CHECK: ret
@ -206,13 +206,13 @@ define void @test_csetm(i32 %lhs, i32 %rhs, i64 %lhs64) {
%val1 = sext i1 %tst1 to i32
store i32 %val1, i32* @var32
; CHECK: cmp {{w[0-9]+}}, {{w[0-9]+}}
; CHECK: csinv {{w[0-9]+}}, wzr, wzr, ne
; CHECK: csetm {{w[0-9]+}}, eq
%rhs64 = sext i32 %rhs to i64
%tst2 = icmp ule i64 %lhs64, %rhs64
%val2 = sext i1 %tst2 to i64
store i64 %val2, i64* @var64
; CHECK: csinv {{x[0-9]+}}, xzr, xzr, hi
; CHECK: csetm {{x[0-9]+}}, ls
ret void
; CHECK: ret

8
test/CodeGen/AArch64/directcond.ll
View File

@ -63,7 +63,7 @@ define i1 @test_setcc_float(float %lhs, float %rhs) {
; CHECK: test_setcc_float
%val = fcmp oeq float %lhs, %rhs
; CHECK: fcmp s0, s1
; CHECK: csinc w0, wzr, wzr, ne
; CHECK: cset w0, eq
; CHECK-NOFP-NOT: fcmp
ret i1 %val
}
@ -72,7 +72,7 @@ define i1 @test_setcc_double(double %lhs, double %rhs) {
; CHECK: test_setcc_double
%val = fcmp oeq double %lhs, %rhs
; CHECK: fcmp d0, d1
; CHECK: csinc w0, wzr, wzr, ne
; CHECK: cset w0, eq
; CHECK-NOFP-NOT: fcmp
ret i1 %val
}
@ -81,7 +81,7 @@ define i1 @test_setcc_i32(i32 %lhs, i32 %rhs) {
; CHECK: test_setcc_i32
%val = icmp ugt i32 %lhs, %rhs
; CHECK: cmp w0, w1
; CHECK: csinc w0, wzr, wzr, ls
; CHECK: cset w0, hi
ret i1 %val
}
@ -89,6 +89,6 @@ define i1 @test_setcc_i64(i64 %lhs, i64 %rhs) {
; CHECK: test_setcc_i64
%val = icmp ne i64 %lhs, %rhs
; CHECK: cmp x0, x1
; CHECK: csinc w0, wzr, wzr, eq
; CHECK: cset w0, ne
ret i1 %val
}

4
test/CodeGen/AArch64/extract.ll
View File

@ -6,7 +6,7 @@ define i64 @ror_i64(i64 %in) {
%left = shl i64 %in, 19
%right = lshr i64 %in, 45
%val5 = or i64 %left, %right
; CHECK: extr {{x[0-9]+}}, x0, x0, #45
; CHECK: ror {{x[0-9]+}}, x0, #45
ret i64 %val5
}
@ -15,7 +15,7 @@ define i32 @ror_i32(i32 %in) {
%left = shl i32 %in, 9
%right = lshr i32 %in, 23
%val5 = or i32 %left, %right
; CHECK: extr {{w[0-9]+}}, w0, w0, #23
; CHECK: ror {{w[0-9]+}}, w0, #23
ret i32 %val5
}

2
test/CodeGen/AArch64/flags-multiuse.ll
View File

@ -16,7 +16,7 @@ define i32 @test_multiflag(i32 %n, i32 %m, i32 %o) {
; CHECK: cmp [[LHS:w[0-9]+]], [[RHS:w[0-9]+]]
%val = zext i1 %test to i32
; CHECK: csinc {{[xw][0-9]+}}, {{xzr|wzr}}, {{xzr|wzr}}, eq
; CHECK: cset {{[xw][0-9]+}}, ne
store i32 %val, i32* @var

10
test/CodeGen/AArch64/fp128.ll
View File

@ -133,7 +133,7 @@ define i1 @test_setcc1() {
%val = fcmp ole fp128 %lhs, %rhs
; CHECK: bl __letf2
; CHECK: cmp w0, #0
; CHECK: csinc w0, wzr, wzr, gt
; CHECK: cset w0, le
ret i1 %val
; CHECK: ret
@ -152,11 +152,11 @@ define i1 @test_setcc2() {
%val = fcmp ugt fp128 %lhs, %rhs
; CHECK: bl __gttf2
; CHECK: cmp w0, #0
; CHECK: csinc [[GT:w[0-9]+]], wzr, wzr, le
; CHECK: cset [[GT:w[0-9]+]], gt
; CHECK: bl __unordtf2
; CHECK: cmp w0, #0
; CHECK: csinc [[UNORDERED:w[0-9]+]], wzr, wzr, eq
; CHECK: cset [[UNORDERED:w[0-9]+]], ne
; CHECK: orr w0, [[UNORDERED]], [[GT]]
@ -176,11 +176,11 @@ define i32 @test_br_cc() {
%cond = fcmp olt fp128 %lhs, %rhs
; CHECK: bl __getf2
; CHECK: cmp w0, #0
; CHECK: csinc [[OGE:w[0-9]+]], wzr, wzr, lt
; CHECK: cset [[OGE:w[0-9]+]], ge
; CHECK: bl __unordtf2
; CHECK: cmp w0, #0
; CHECK: csinc [[UNORDERED:w[0-9]+]], wzr, wzr, eq
; CHECK: cset [[UNORDERED:w[0-9]+]], ne
; CHECK: orr [[UGE:w[0-9]+]], [[UNORDERED]], [[OGE]]
; CHECK: cbnz [[UGE]], [[RET29:.LBB[0-9]+_[0-9]+]]

20
test/CodeGen/AArch64/neon-select_cc.ll
View File

@ -4,7 +4,7 @@ define <8x i8> @test_select_cc_v8i8_i8(i8 %a, i8 %b, <8x i8> %c, <8x i8> %d ) {
; CHECK-LABEL: test_select_cc_v8i8_i8:
; CHECK: and w0, w0, #0xff
; CHECK-NEXT: cmp w0, w1, uxtb
; CHECK-NEXT: csinv w0, wzr, wzr, ne
; CHECK-NEXT: csetm w0, eq
; CHECK-NEXT: dup v{{[0-9]+}}.8b, w0
; CHECK-NEXT: bsl v{{[0-9]+}}.8b, v0.8b, v1.8b
%cmp31 = icmp eq i8 %a, %b
@ -35,7 +35,7 @@ define <16x i8> @test_select_cc_v16i8_i8(i8 %a, i8 %b, <16x i8> %c, <16x i8> %d
; CHECK-LABEL: test_select_cc_v16i8_i8:
; CHECK: and w0, w0, #0xff
; CHECK-NEXT: cmp w0, w1, uxtb
; CHECK-NEXT: csinv w0, wzr, wzr, ne
; CHECK-NEXT: csetm w0, eq
; CHECK-NEXT: dup v{{[0-9]+}}.16b, w0
; CHECK-NEXT: bsl v{{[0-9]+}}.16b, v0.16b, v1.16b
%cmp31 = icmp eq i8 %a, %b
@ -67,7 +67,7 @@ define <4x i16> @test_select_cc_v4i16(i16 %a, i16 %b, <4x i16> %c, <4x i16> %d )
; CHECK-LABEL: test_select_cc_v4i16:
; CHECK: and w0, w0, #0xffff
; CHECK-NEXT: cmp w0, w1, uxth
; CHECK-NEXT: csinv w0, wzr, wzr, ne
; CHECK-NEXT: csetm w0, eq
; CHECK-NEXT: dup v{{[0-9]+}}.4h, w0
; CHECK-NEXT: bsl v{{[0-9]+}}.8b, v0.8b, v1.8b
%cmp31 = icmp eq i16 %a, %b
@ -79,7 +79,7 @@ define <8x i16> @test_select_cc_v8i16(i16 %a, i16 %b, <8x i16> %c, <8x i16> %d )
; CHECK-LABEL: test_select_cc_v8i16:
; CHECK: and w0, w0, #0xffff
; CHECK-NEXT: cmp w0, w1, uxth
; CHECK-NEXT: csinv w0, wzr, wzr, ne
; CHECK-NEXT: csetm w0, eq
; CHECK-NEXT: dup v{{[0-9]+}}.8h, w0
; CHECK-NEXT: bsl v{{[0-9]+}}.16b, v0.16b, v1.16b
%cmp31 = icmp eq i16 %a, %b
@ -90,7 +90,7 @@ define <8x i16> @test_select_cc_v8i16(i16 %a, i16 %b, <8x i16> %c, <8x i16> %d )
define <2x i32> @test_select_cc_v2i32(i32 %a, i32 %b, <2x i32> %c, <2x i32> %d ) {
; CHECK-LABEL: test_select_cc_v2i32:
; CHECK: cmp w0, w1, uxtw
; CHECK-NEXT: csinv w0, wzr, wzr, ne
; CHECK-NEXT: csetm w0, eq
; CHECK-NEXT: dup v{{[0-9]+}}.2s, w0
; CHECK-NEXT: bsl v{{[0-9]+}}.8b, v0.8b, v1.8b
%cmp31 = icmp eq i32 %a, %b
@ -101,7 +101,7 @@ define <2x i32> @test_select_cc_v2i32(i32 %a, i32 %b, <2x i32> %c, <2x i32> %d )
define <4x i32> @test_select_cc_v4i32(i32 %a, i32 %b, <4x i32> %c, <4x i32> %d ) {
; CHECK-LABEL: test_select_cc_v4i32:
; CHECK: cmp w0, w1, uxtw
; CHECK-NEXT: csinv w0, wzr, wzr, ne
; CHECK-NEXT: csetm w0, eq
; CHECK-NEXT: dup v{{[0-9]+}}.4s, w0
; CHECK-NEXT: bsl v{{[0-9]+}}.16b, v0.16b, v1.16b
%cmp31 = icmp eq i32 %a, %b
@ -112,7 +112,7 @@ define <4x i32> @test_select_cc_v4i32(i32 %a, i32 %b, <4x i32> %c, <4x i32> %d )
define <1x i64> @test_select_cc_v1i64(i64 %a, i64 %b, <1x i64> %c, <1x i64> %d ) {
; CHECK-LABEL: test_select_cc_v1i64:
; CHECK: cmp x0, x1
; CHECK-NEXT: csinv x0, xzr, xzr, ne
; CHECK-NEXT: csetm x0, eq
; CHECK-NEXT: fmov d{{[0-9]+}}, x0
; CHECK-NEXT: bsl v{{[0-9]+}}.8b, v0.8b, v1.8b
%cmp31 = icmp eq i64 %a, %b
@ -123,7 +123,7 @@ define <1x i64> @test_select_cc_v1i64(i64 %a, i64 %b, <1x i64> %c, <1x i64> %d )
define <2x i64> @test_select_cc_v2i64(i64 %a, i64 %b, <2x i64> %c, <2x i64> %d ) {
; CHECK-LABEL: test_select_cc_v2i64:
; CHECK: cmp x0, x1
; CHECK-NEXT: csinv x0, xzr, xzr, ne
; CHECK-NEXT: csetm x0, eq
; CHECK-NEXT: dup v{{[0-9]+}}.2d, x0
; CHECK-NEXT: bsl v{{[0-9]+}}.16b, v0.16b, v1.16b
%cmp31 = icmp eq i64 %a, %b
@ -163,7 +163,7 @@ define <4x float> @test_select_cc_v4f32(float %a, float %b, <4x float> %c, <4x f
define <4x float> @test_select_cc_v4f32_icmp(i32 %a, i32 %b, <4x float> %c, <4x float> %d ) {
; CHECK-LABEL: test_select_cc_v4f32_icmp:
; CHECK: cmp w0, w1, uxtw
; CHECK: csinv w0, wzr, wzr, ne
; CHECK: csetm w0, eq
; CHECK-NEXT: dup v{{[0-9]+}}.4s, w0
; CHECK-NEXT: bsl v{{[0-9]+}}.16b, v0.16b, v1.16b
%cmp31 = icmp eq i32 %a, %b
@ -183,7 +183,7 @@ define <1 x double> @test_select_cc_v1f64(double %a, double %b, <1 x double> %c,
define <1 x double> @test_select_cc_v1f64_icmp(i64 %a, i64 %b, <1 x double> %c, <1 x double> %d ) {
; CHECK-LABEL: test_select_cc_v1f64_icmp:
; CHECK: cmp x0, x1
; CHECK-NEXT: csinv x0, xzr, xzr, ne
; CHECK-NEXT: csetm x0, eq
; CHECK-NEXT: fmov d{{[0-9]+}}, x0
; CHECK-NEXT: bsl v{{[0-9]+}}.8b, v0.8b, v1.8b
%cmp31 = icmp eq i64 %a, %b

16
test/CodeGen/ARM64/atomic-128.ll
View File

@ -86,9 +86,9 @@ define void @fetch_and_min(i128* %p, i128 %bits) {
; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
; CHECK: ldaxp [[DEST_REGLO:x[0-9]+]], [[DEST_REGHI:x[0-9]+]], [x0]
; CHECK: cmp [[DEST_REGLO]], x2
; CHECK: csinc [[LOCMP:w[0-9]+]], wzr, wzr, hi
; CHECK: cset [[LOCMP:w[0-9]+]], ls
; CHECK: cmp [[DEST_REGHI:x[0-9]+]], x3
; CHECK: csinc [[HICMP:w[0-9]+]], wzr, wzr, gt
; CHECK: cset [[HICMP:w[0-9]+]], le
; CHECK: csel [[CMP:w[0-9]+]], [[LOCMP]], [[HICMP]], eq
; CHECK: cmp [[CMP]], #0
; CHECK-DAG: csel [[SCRATCH_REGHI:x[0-9]+]], [[DEST_REGHI]], x3, ne
@ -108,9 +108,9 @@ define void @fetch_and_max(i128* %p, i128 %bits) {
; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
; CHECK: ldaxp [[DEST_REGLO:x[0-9]+]], [[DEST_REGHI:x[0-9]+]], [x0]
; CHECK: cmp [[DEST_REGLO]], x2
; CHECK: csinc [[LOCMP:w[0-9]+]], wzr, wzr, ls
; CHECK: cset [[LOCMP:w[0-9]+]], hi
; CHECK: cmp [[DEST_REGHI:x[0-9]+]], x3
; CHECK: csinc [[HICMP:w[0-9]+]], wzr, wzr, le
; CHECK: cset [[HICMP:w[0-9]+]], gt
; CHECK: csel [[CMP:w[0-9]+]], [[LOCMP]], [[HICMP]], eq
; CHECK: cmp [[CMP]], #0
; CHECK-DAG: csel [[SCRATCH_REGHI:x[0-9]+]], [[DEST_REGHI]], x3, ne
@ -130,9 +130,9 @@ define void @fetch_and_umin(i128* %p, i128 %bits) {
; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
; CHECK: ldaxp [[DEST_REGLO:x[0-9]+]], [[DEST_REGHI:x[0-9]+]], [x0]
; CHECK: cmp [[DEST_REGLO]], x2
; CHECK: csinc [[LOCMP:w[0-9]+]], wzr, wzr, hi
; CHECK: cset [[LOCMP:w[0-9]+]], ls
; CHECK: cmp [[DEST_REGHI:x[0-9]+]], x3
; CHECK: csinc [[HICMP:w[0-9]+]], wzr, wzr, hi
; CHECK: cset [[HICMP:w[0-9]+]], ls
; CHECK: csel [[CMP:w[0-9]+]], [[LOCMP]], [[HICMP]], eq
; CHECK: cmp [[CMP]], #0
; CHECK-DAG: csel [[SCRATCH_REGHI:x[0-9]+]], [[DEST_REGHI]], x3, ne
@ -152,9 +152,9 @@ define void @fetch_and_umax(i128* %p, i128 %bits) {
; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
; CHECK: ldaxp [[DEST_REGLO:x[0-9]+]], [[DEST_REGHI:x[0-9]+]], [x0]
; CHECK: cmp [[DEST_REGLO]], x2
; CHECK: csinc [[LOCMP:w[0-9]+]], wzr, wzr, ls
; CHECK: cset [[LOCMP:w[0-9]+]], hi
; CHECK: cmp [[DEST_REGHI:x[0-9]+]], x3
; CHECK: csinc [[HICMP:w[0-9]+]], wzr, wzr, ls
; CHECK: cset [[HICMP:w[0-9]+]], hi
; CHECK: csel [[CMP:w[0-9]+]], [[LOCMP]], [[HICMP]], eq
; CHECK: cmp [[CMP]], #0
; CHECK-DAG: csel [[SCRATCH_REGHI:x[0-9]+]], [[DEST_REGHI]], x3, ne

2
test/CodeGen/ARM64/cast-opt.ll
View File

@ -7,7 +7,7 @@
define zeroext i8 @foo(i32 %i1, i32 %i2) {
; CHECK-LABEL: foo:
; CHECK: csinc
; CHECK: cset
; CHECK-NOT: and
entry:
%idxprom = sext i32 %i1 to i64

41
test/CodeGen/ARM64/csel.ll
View File

@ -2,9 +2,8 @@
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32:64"
target triple = "arm64-unknown-unknown"
; CHECK: foo1
; CHECK: csinc w{{[0-9]+}}, w[[REG:[0-9]+]],
; CHECK: w[[REG]], eq
; CHECK-LABEL: foo1
; CHECK: cinc w{{[0-9]+}}, w{{[0-9]+}}, ne
define i32 @foo1(i32 %b, i32 %c) nounwind readnone ssp {
entry:
%not.tobool = icmp ne i32 %c, 0
@ -14,9 +13,8 @@ entry:
ret i32 %add1
}
; CHECK: foo2
; CHECK: csneg w{{[0-9]+}}, w[[REG:[0-9]+]],
; CHECK: w[[REG]], eq
; CHECK-LABEL: foo2
; CHECK: cneg w{{[0-9]+}}, w{{[0-9]+}}, ne
define i32 @foo2(i32 %b, i32 %c) nounwind readnone ssp {
entry:
%mul = sub i32 0, %b
@ -26,9 +24,8 @@ entry:
ret i32 %add
}
; CHECK: foo3
; CHECK: csinv w{{[0-9]+}}, w[[REG:[0-9]+]],
; CHECK: w[[REG]], eq
; CHECK-LABEL: foo3
; CHECK: cinv w{{[0-9]+}}, w{{[0-9]+}}, ne
define i32 @foo3(i32 %b, i32 %c) nounwind readnone ssp {
entry:
%not.tobool = icmp ne i32 %c, 0
@ -40,8 +37,8 @@ entry:
; rdar://11632325
define i32@foo4(i32 %a) nounwind ssp {
; CHECK: foo4
; CHECK: csneg
; CHECK-LABEL: foo4
; CHECK: cneg
; CHECK-NEXT: ret
%cmp = icmp sgt i32 %a, -1
%neg = sub nsw i32 0, %a
@ -51,9 +48,9 @@ define i32@foo4(i32 %a) nounwind ssp {
define i32@foo5(i32 %a, i32 %b) nounwind ssp {
entry:
; CHECK: foo5
; CHECK-LABEL: foo5
; CHECK: subs
; CHECK-NEXT: csneg
; CHECK-NEXT: cneg
; CHECK-NEXT: ret
%sub = sub nsw i32 %a, %b
%cmp = icmp sgt i32 %sub, -1
@ -64,7 +61,7 @@ entry:
; make sure we can handle branch instruction in optimizeCompare.
define i32@foo6(i32 %a, i32 %b) nounwind ssp {
; CHECK: foo6
; CHECK-LABEL: foo6
; CHECK: b
%sub = sub nsw i32 %a, %b
%cmp = icmp sgt i32 %sub, 0
@ -116,7 +113,7 @@ entry:
; CHECK-LABEL: foo9:
; CHECK: cmp w0, #0
; CHECK: orr w[[REG:[0-9]+]], wzr, #0x4
; CHECK: csinv w0, w[[REG]], w[[REG]], ne
; CHECK: cinv w0, w[[REG]], eq
%tobool = icmp ne i32 %v, 0
%cond = select i1 %tobool, i32 4, i32 -5
ret i32 %cond
@ -127,7 +124,7 @@ entry:
; CHECK-LABEL: foo10:
; CHECK: cmp x0, #0
; CHECK: orr w[[REG:[0-9]+]], wzr, #0x4
; CHECK: csinv x0, x[[REG]], x[[REG]], ne
; CHECK: cinv x0, x[[REG]], eq
%tobool = icmp ne i64 %v, 0
%cond = select i1 %tobool, i64 4, i64 -5
ret i64 %cond
@ -138,7 +135,7 @@ entry:
; CHECK-LABEL: foo11:
; CHECK: cmp w0, #0
; CHECK: orr w[[REG:[0-9]+]], wzr, #0x4
; CHECK: csneg w0, w[[REG]], w[[REG]], ne
; CHECK: cneg w0, w[[REG]], eq
%tobool = icmp ne i32 %v, 0
%cond = select i1 %tobool, i32 4, i32 -4
ret i32 %cond
@ -149,7 +146,7 @@ entry:
; CHECK-LABEL: foo12:
; CHECK: cmp x0, #0
; CHECK: orr w[[REG:[0-9]+]], wzr, #0x4
; CHECK: csneg x0, x[[REG]], x[[REG]], ne
; CHECK: cneg x0, x[[REG]], eq
%tobool = icmp ne i64 %v, 0
%cond = select i1 %tobool, i64 4, i64 -4
ret i64 %cond
@ -182,7 +179,7 @@ entry:
; CHECK-LABEL: foo15:
; CHECK: cmp w0, w1
; CHECK: orr w[[REG:[0-9]+]], wzr, #0x1
; CHECK: csinc w0, w[[REG]], w[[REG]], le
; CHECK: cinc w0, w[[REG]], gt
%cmp = icmp sgt i32 %a, %b
%. = select i1 %cmp, i32 2, i32 1
ret i32 %.
@ -193,7 +190,7 @@ entry:
; CHECK-LABEL: foo16:
; CHECK: cmp w0, w1
; CHECK: orr w[[REG:[0-9]+]], wzr, #0x1
; CHECK: csinc w0, w[[REG]], w[[REG]], gt
; CHECK: cinc w0, w[[REG]], le
%cmp = icmp sgt i32 %a, %b
%. = select i1 %cmp, i32 1, i32 2
ret i32 %.
@ -204,7 +201,7 @@ entry:
; CHECK-LABEL: foo17:
; CHECK: cmp x0, x1
; CHECK: orr w[[REG:[0-9]+]], wzr, #0x1
; CHECK: csinc x0, x[[REG]], x[[REG]], le
; CHECK: cinc x0, x[[REG]], gt
%cmp = icmp sgt i64 %a, %b
%. = select i1 %cmp, i64 2, i64 1
ret i64 %.
@ -215,7 +212,7 @@ entry:
; CHECK-LABEL: foo18:
; CHECK: cmp x0, x1
; CHECK: orr w[[REG:[0-9]+]], wzr, #0x1
; CHECK: csinc x0, x[[REG]], x[[REG]], gt
; CHECK: cinc x0, x[[REG]], le
%cmp = icmp sgt i64 %a, %b
%. = select i1 %cmp, i64 1, i64 2
ret i64 %.

4
test/CodeGen/ARM64/extract.ll
View File

@ -6,7 +6,7 @@ define i64 @ror_i64(i64 %in) {
%left = shl i64 %in, 19
%right = lshr i64 %in, 45
%val5 = or i64 %left, %right
; CHECK: extr {{x[0-9]+}}, x0, x0, #45
; CHECK: ror {{x[0-9]+}}, x0, #45
ret i64 %val5
}
@ -15,7 +15,7 @@ define i32 @ror_i32(i32 %in) {
%left = shl i32 %in, 9
%right = lshr i32 %in, 23
%val5 = or i32 %left, %right
; CHECK: extr {{w[0-9]+}}, w0, w0, #23
; CHECK: ror {{w[0-9]+}}, w0, #23
ret i32 %val5
}

64
test/CodeGen/ARM64/fast-isel-fcmp.ll
View File

@ -2,144 +2,144 @@
define zeroext i1 @fcmp_float1(float %a) nounwind ssp {
entry:
; CHECK: @fcmp_float1
; CHECK-LABEL: @fcmp_float1
; CHECK: fcmp s0, #0.0
; CHECK: csinc w{{[0-9]+}}, wzr, wzr, eq
; CHECK: cset w{{[0-9]+}}, ne
%cmp = fcmp une float %a, 0.000000e+00
ret i1 %cmp
}
define zeroext i1 @fcmp_float2(float %a, float %b) nounwind ssp {
entry:
; CHECK: @fcmp_float2
; CHECK-LABEL: @fcmp_float2
; CHECK: fcmp s0, s1
; CHECK: csinc w{{[0-9]+}}, wzr, wzr, eq
; CHECK: cset w{{[0-9]+}}, ne
%cmp = fcmp une float %a, %b
ret i1 %cmp
}
define zeroext i1 @fcmp_double1(double %a) nounwind ssp {
entry:
; CHECK: @fcmp_double1
; CHECK-LABEL: @fcmp_double1
; CHECK: fcmp d0, #0.0
; CHECK: csinc w{{[0-9]+}}, wzr, wzr, eq
; CHECK: cset w{{[0-9]+}}, ne
%cmp = fcmp une double %a, 0.000000e+00
ret i1 %cmp
}
define zeroext i1 @fcmp_double2(double %a, double %b) nounwind ssp {
entry:
; CHECK: @fcmp_double2
; CHECK-LABEL: @fcmp_double2
; CHECK: fcmp d0, d1
; CHECK: csinc w{{[0-9]+}}, wzr, wzr, eq
; CHECK: cset w{{[0-9]+}}, ne
%cmp = fcmp une double %a, %b
ret i1 %cmp
}
; Check each fcmp condition
define float @fcmp_oeq(float %a, float %b) nounwind ssp {
; CHECK: @fcmp_oeq
; CHECK-LABEL: @fcmp_oeq
; CHECK: fcmp s0, s1
; CHECK: csinc w{{[0-9]+}}, wzr, wzr, ne
; CHECK: cset w{{[0-9]+}}, eq
%cmp = fcmp oeq float %a, %b
%conv = uitofp i1 %cmp to float
ret float %conv
}
define float @fcmp_ogt(float %a, float %b) nounwind ssp {
; CHECK: @fcmp_ogt
; CHECK-LABEL: @fcmp_ogt
; CHECK: fcmp s0, s1
; CHECK: csinc w{{[0-9]+}}, wzr, wzr, le
; CHECK: cset w{{[0-9]+}}, gt
%cmp = fcmp ogt float %a, %b
%conv = uitofp i1 %cmp to float
ret float %conv
}
define float @fcmp_oge(float %a, float %b) nounwind ssp {
; CHECK: @fcmp_oge
; CHECK-LABEL: @fcmp_oge
; CHECK: fcmp s0, s1
; CHECK: csinc w{{[0-9]+}}, wzr, wzr, lt
; CHECK: cset w{{[0-9]+}}, ge
%cmp = fcmp oge float %a, %b
%conv = uitofp i1 %cmp to float
ret float %conv
}
define float @fcmp_olt(float %a, float %b) nounwind ssp {
; CHECK: @fcmp_olt
; CHECK-LABEL: @fcmp_olt
; CHECK: fcmp s0, s1
; CHECK: csinc w{{[0-9]+}}, wzr, wzr, pl
; CHECK: cset w{{[0-9]+}}, mi
%cmp = fcmp olt float %a, %b
%conv = uitofp i1 %cmp to float
ret float %conv
}
define float @fcmp_ole(float %a, float %b) nounwind ssp {
; CHECK: @fcmp_ole
; CHECK-LABEL: @fcmp_ole
; CHECK: fcmp s0, s1
; CHECK: csinc w{{[0-9]+}}, wzr, wzr, hi
; CHECK: cset w{{[0-9]+}}, ls
%cmp = fcmp ole float %a, %b
%conv = uitofp i1 %cmp to float
ret float %conv
}
define float @fcmp_ord(float %a, float %b) nounwind ssp {
; CHECK: @fcmp_ord
; CHECK-LABEL: @fcmp_ord
; CHECK: fcmp s0, s1
; CHECK: csinc {{w[0-9]+}}, wzr, wzr, vs
; CHECK: cset {{w[0-9]+}}, vc
%cmp = fcmp ord float %a, %b
%conv = uitofp i1 %cmp to float
ret float %conv
}
define float @fcmp_uno(float %a, float %b) nounwind ssp {
; CHECK: @fcmp_uno
; CHECK-LABEL: @fcmp_uno
; CHECK: fcmp s0, s1
; CHECK: csinc {{w[0-9]+}}, wzr, wzr, vc
; CHECK: cset {{w[0-9]+}}, vs
%cmp = fcmp uno float %a, %b
%conv = uitofp i1 %cmp to float
ret float %conv
}
define float @fcmp_ugt(float %a, float %b) nounwind ssp {
; CHECK: @fcmp_ugt
; CHECK-LABEL: @fcmp_ugt
; CHECK: fcmp s0, s1
; CHECK: csinc {{w[0-9]+}}, wzr, wzr, ls
; CHECK: cset {{w[0-9]+}}, hi
%cmp = fcmp ugt float %a, %b
%conv = uitofp i1 %cmp to float
ret float %conv
}
define float @fcmp_uge(float %a, float %b) nounwind ssp {
; CHECK: @fcmp_uge
; CHECK-LABEL: @fcmp_uge
; CHECK: fcmp s0, s1
; CHECK: csinc {{w[0-9]+}}, wzr, wzr, mi
; CHECK: cset {{w[0-9]+}}, pl
%cmp = fcmp uge float %a, %b
%conv = uitofp i1 %cmp to float
ret float %conv
}
define float @fcmp_ult(float %a, float %b) nounwind ssp {
; CHECK: @fcmp_ult
; CHECK-LABEL: @fcmp_ult
; CHECK: fcmp s0, s1
; CHECK: csinc {{w[0-9]+}}, wzr, wzr, ge
; CHECK: cset {{w[0-9]+}}, lt
%cmp = fcmp ult float %a, %b
%conv = uitofp i1 %cmp to float
ret float %conv
}
define float @fcmp_ule(float %a, float %b) nounwind ssp {
; CHECK: @fcmp_ule
; CHECK-LABEL: @fcmp_ule
; CHECK: fcmp s0, s1
; CHECK: csinc {{w[0-9]+}}, wzr, wzr, gt
; CHECK: cset {{w[0-9]+}}, le
%cmp = fcmp ule float %a, %b
%conv = uitofp i1 %cmp to float
ret float %conv
}
define float @fcmp_une(float %a, float %b) nounwind ssp {
; CHECK: @fcmp_une
; CHECK-LABEL: @fcmp_une
; CHECK: fcmp s0, s1
; CHECK: csinc {{w[0-9]+}}, wzr, wzr, eq
; CHECK: cset {{w[0-9]+}}, ne
%cmp = fcmp une float %a, %b
%conv = uitofp i1 %cmp to float
ret float %conv

40
test/CodeGen/ARM64/fast-isel-icmp.ll
View File

@ -4,7 +4,7 @@ define i32 @icmp_eq_imm(i32 %a) nounwind ssp {
entry:
; CHECK: icmp_eq_imm
; CHECK: cmp w0, #31
; CHECK: csinc w0, wzr, wzr, ne
; CHECK: cset w0, eq
%cmp = icmp eq i32 %a, 31
%conv = zext i1 %cmp to i32
ret i32 %conv
@ -14,7 +14,7 @@ define i32 @icmp_eq_neg_imm(i32 %a) nounwind ssp {
entry:
; CHECK: icmp_eq_neg_imm
; CHECK: cmn w0, #7
; CHECK: csinc w0, wzr, wzr, ne
; CHECK: cset w0, eq
%cmp = icmp eq i32 %a, -7
%conv = zext i1 %cmp to i32
ret i32 %conv
@ -24,7 +24,7 @@ define i32 @icmp_eq(i32 %a, i32 %b) nounwind ssp {
entry:
; CHECK: icmp_eq
; CHECK: cmp w0, w1
; CHECK: csinc w0, wzr, wzr, ne
; CHECK: cset w0, eq
%cmp = icmp eq i32 %a, %b
%conv = zext i1 %cmp to i32
ret i32 %conv
@ -34,7 +34,7 @@ define i32 @icmp_ne(i32 %a, i32 %b) nounwind ssp {
entry:
; CHECK: icmp_ne
; CHECK: cmp w0, w1
; CHECK: csinc w0, wzr, wzr, eq
; CHECK: cset w0, ne
%cmp = icmp ne i32 %a, %b
%conv = zext i1 %cmp to i32
ret i32 %conv
@ -44,7 +44,7 @@ define i32 @icmp_ugt(i32 %a, i32 %b) nounwind ssp {
entry:
; CHECK: icmp_ugt
; CHECK: cmp w0, w1
; CHECK: csinc w0, wzr, wzr, ls
; CHECK: cset w0, hi
%cmp = icmp ugt i32 %a, %b
%conv = zext i1 %cmp to i32
ret i32 %conv
@ -54,7 +54,7 @@ define i32 @icmp_uge(i32 %a, i32 %b) nounwind ssp {
entry:
; CHECK: icmp_uge
; CHECK: cmp w0, w1
; CHECK: csinc w0, wzr, wzr, lo
; CHECK: cset w0, hs
%cmp = icmp uge i32 %a, %b
%conv = zext i1 %cmp to i32
ret i32 %conv
@ -64,7 +64,7 @@ define i32 @icmp_ult(i32 %a, i32 %b) nounwind ssp {
entry:
; CHECK: icmp_ult
; CHECK: cmp w0, w1
; CHECK: csinc w0, wzr, wzr, hs
; CHECK: cset w0, lo
%cmp = icmp ult i32 %a, %b
%conv = zext i1 %cmp to i32
ret i32 %conv
@ -74,7 +74,7 @@ define i32 @icmp_ule(i32 %a, i32 %b) nounwind ssp {
entry:
; CHECK: icmp_ule
; CHECK: cmp w0, w1
; CHECK: csinc w0, wzr, wzr, hi
; CHECK: cset w0, ls
%cmp = icmp ule i32 %a, %b
%conv = zext i1 %cmp to i32
ret i32 %conv
@ -84,7 +84,7 @@ define i32 @icmp_sgt(i32 %a, i32 %b) nounwind ssp {
entry:
; CHECK: icmp_sgt
; CHECK: cmp w0, w1
; CHECK: csinc w0, wzr, wzr, le
; CHECK: cset w0, gt
%cmp = icmp sgt i32 %a, %b
%conv = zext i1 %cmp to i32
ret i32 %conv
@ -94,7 +94,7 @@ define i32 @icmp_sge(i32 %a, i32 %b) nounwind ssp {
entry:
; CHECK: icmp_sge
; CHECK: cmp w0, w1
; CHECK: csinc w0, wzr, wzr, lt
; CHECK: cset w0, ge
%cmp = icmp sge i32 %a, %b
%conv = zext i1 %cmp to i32
ret i32 %conv
@ -104,7 +104,7 @@ define i32 @icmp_slt(i32 %a, i32 %b) nounwind ssp {
entry:
; CHECK: icmp_slt
; CHECK: cmp w0, w1
; CHECK: csinc w0, wzr, wzr, ge
; CHECK: cset w0, lt
%cmp = icmp slt i32 %a, %b
%conv = zext i1 %cmp to i32
ret i32 %conv
@ -114,7 +114,7 @@ define i32 @icmp_sle(i32 %a, i32 %b) nounwind ssp {
entry:
; CHECK: icmp_sle
; CHECK: cmp w0, w1
; CHECK: csinc w0, wzr, wzr, gt
; CHECK: cset w0, le
%cmp = icmp sle i32 %a, %b
%conv = zext i1 %cmp to i32
ret i32 %conv
@ -124,7 +124,7 @@ define i32 @icmp_i64(i64 %a, i64 %b) nounwind ssp {
entry:
; CHECK: icmp_i64
; CHECK: cmp x0, x1
; CHECK: csinc w{{[0-9]+}}, wzr, wzr, gt
; CHECK: cset w{{[0-9]+}}, le
%cmp = icmp sle i64 %a, %b
%conv = zext i1 %cmp to i32
ret i32 %conv
@ -136,7 +136,7 @@ entry:
; CHECK: sxth w0, w0
; CHECK: sxth w1, w1
; CHECK: cmp w0, w1
; CHECK: csinc w0, wzr, wzr, ne
; CHECK: cset w0, eq
%cmp = icmp eq i16 %a, %b
ret i1 %cmp
}
@ -147,7 +147,7 @@ entry:
; CHECK: sxtb w0, w0
; CHECK: sxtb w1, w1
; CHECK: cmp w0, w1
; CHECK: csinc w0, wzr, wzr, ne
; CHECK: cset w0, eq
%cmp = icmp eq i8 %a, %b
ret i1 %cmp
}
@ -158,7 +158,7 @@ entry:
; CHECK: uxth w0, w0
; CHECK: uxth w1, w1
; CHECK: cmp w0, w1
; CHECK: csinc w0, wzr, wzr, hs
; CHECK: cset w0, lo
%cmp = icmp ult i16 %a, %b
%conv2 = zext i1 %cmp to i32
ret i32 %conv2
@ -170,7 +170,7 @@ entry:
; CHECK: sxtb w0, w0
; CHECK: sxtb w1, w1
; CHECK: cmp w0, w1
; CHECK: csinc w0, wzr, wzr, le
; CHECK: cset w0, gt
%cmp = icmp sgt i8 %a, %b
%conv2 = zext i1 %cmp to i32
ret i32 %conv2
@ -182,7 +182,7 @@ entry:
; CHECK: icmp_i16_signed_const
; CHECK: sxth w0, w0
; CHECK: cmn w0, #233
; CHECK: csinc w0, wzr, wzr, ge
; CHECK: cset w0, lt
; CHECK: and w0, w0, #0x1
%cmp = icmp slt i16 %a, -233
%conv2 = zext i1 %cmp to i32
@ -194,7 +194,7 @@ entry:
; CHECK: icmp_i8_signed_const
; CHECK: sxtb w0, w0
; CHECK: cmp w0, #124
; CHECK: csinc w0, wzr, wzr, le
; CHECK: cset w0, gt
; CHECK: and w0, w0, #0x1
%cmp = icmp sgt i8 %a, 124
%conv2 = zext i1 %cmp to i32
@ -206,7 +206,7 @@ entry:
; CHECK: icmp_i1_unsigned_const
; CHECK: and w0, w0, #0x1
; CHECK: cmp w0, #0
; CHECK: csinc w0, wzr, wzr, hs
; CHECK: cset w0, lo
; CHECK: and w0, w0, #0x1
%cmp = icmp ult i1 %a, 0
%conv2 = zext i1 %cmp to i32

8
test/CodeGen/ARM64/fcmp-opt.ll
View File

@ -5,7 +5,7 @@ define i1 @fcmp_float1(float %a) nounwind ssp {
entry:
; CHECK-LABEL: @fcmp_float1
; CHECK: fcmp s0, #0.0
; CHECK: csinc w0, wzr, wzr, eq
; CHECK: cset w0, ne
%cmp = fcmp une float %a, 0.000000e+00
ret i1 %cmp
}
@ -14,7 +14,7 @@ define i1 @fcmp_float2(float %a, float %b) nounwind ssp {
entry:
; CHECK-LABEL: @fcmp_float2
; CHECK: fcmp s0, s1
; CHECK: csinc w0, wzr, wzr, eq
; CHECK: cset w0, ne
%cmp = fcmp une float %a, %b
ret i1 %cmp
}
@ -23,7 +23,7 @@ define i1 @fcmp_double1(double %a) nounwind ssp {
entry:
; CHECK-LABEL: @fcmp_double1
; CHECK: fcmp d0, #0.0
; CHECK: csinc w0, wzr, wzr, eq
; CHECK: cset w0, ne
%cmp = fcmp une double %a, 0.000000e+00
ret i1 %cmp
}
@ -32,7 +32,7 @@ define i1 @fcmp_double2(double %a, double %b) nounwind ssp {
entry:
; CHECK-LABEL: @fcmp_double2
; CHECK: fcmp d0, d1
; CHECK: csinc w0, wzr, wzr, eq
; CHECK: cset w0, ne
%cmp = fcmp une double %a, %b
ret i1 %cmp
}

10
test/CodeGen/ARM64/fp128.ll
View File

@ -133,7 +133,7 @@ define i1 @test_setcc1() {
%val = fcmp ole fp128 %lhs, %rhs
; CHECK: bl __letf2
; CHECK: cmp w0, #0
; CHECK: csinc w0, wzr, wzr, gt
; CHECK: cset w0, le
ret i1 %val
; CHECK: ret
@ -150,11 +150,11 @@ define i1 @test_setcc2() {
%val = fcmp ugt fp128 %lhs, %rhs
; CHECK: bl __gttf2
; CHECK: cmp w0, #0
; CHECK: csinc [[GT:w[0-9]+]], wzr, wzr, le
; CHECK: cset [[GT:w[0-9]+]], gt
; CHECK: bl __unordtf2
; CHECK: cmp w0, #0
; CHECK: csinc [[UNORDERED:w[0-9]+]], wzr, wzr, eq
; CHECK: cset [[UNORDERED:w[0-9]+]], ne
; CHECK: orr w0, [[UNORDERED]], [[GT]]
ret i1 %val
@ -173,11 +173,11 @@ define i32 @test_br_cc() {
%cond = fcmp olt fp128 %lhs, %rhs
; CHECK: bl __getf2
; CHECK: cmp w0, #0
; CHECK: csinc [[OGE:w[0-9]+]], wzr, wzr, lt
; CHECK: cset [[OGE:w[0-9]+]], ge
; CHECK: bl __unordtf2
; CHECK: cmp w0, #0
; CHECK: csinc [[UNORDERED:w[0-9]+]], wzr, wzr, eq
; CHECK: cset [[UNORDERED:w[0-9]+]], ne
; CHECK: orr [[UGE:w[0-9]+]], [[UNORDERED]], [[OGE]]
; CHECK: cbnz [[UGE]], [[RET29:.LBB[0-9]+_[0-9]+]]

2
test/CodeGen/ARM64/icmp-opt.ll
View File

@ -10,7 +10,7 @@ entry:
; CHECK-LABEL: t1:
; CHECK-NOT: movn
; CHECK: cmp x0, #0
; CHECK: csinc w0, wzr, wzr, lt
; CHECK: cset w0, ge
%cmp = icmp sgt i64 %a, -1
%conv = zext i1 %cmp to i32
ret i32 %conv

2
test/CodeGen/ARM64/neon-v1i1-setcc.ll
View File

@ -7,7 +7,7 @@
define i64 @test_sext_extr_cmp_0(<1 x i64> %v1, <1 x i64> %v2) {
; CHECK-LABEL: test_sext_extr_cmp_0:
; CHECK: cmp {{x[0-9]+}}, {{x[0-9]+}}
; CHECK: csinc
; CHECK: cset
%1 = icmp sge <1 x i64> %v1, %v2
%2 = extractelement <1 x i1> %1, i32 0
%vget_lane = sext i1 %2 to i64

24
test/CodeGen/ARM64/xaluo.ll
View File

@ -7,7 +7,7 @@ define i1 @saddo.i32(i32 %v1, i32 %v2, i32* %res) {
entry:
; CHECK-LABEL: saddo.i32
; CHECK: adds w8, w0, w1
; CHECK-NEXT: csinc w0, wzr, wzr, vc
; CHECK-NEXT: cset w0, vs
%t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2)
%val = extractvalue {i32, i1} %t, 0
%obit = extractvalue {i32, i1} %t, 1
@ -19,7 +19,7 @@ define i1 @saddo.i64(i64 %v1, i64 %v2, i64* %res) {
entry:
; CHECK-LABEL: saddo.i64
; CHECK: adds x8, x0, x1
; CHECK-NEXT: csinc w0, wzr, wzr, vc
; CHECK-NEXT: cset w0, vs
%t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 %v2)
%val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1
@ -31,7 +31,7 @@ define i1 @uaddo.i32(i32 %v1, i32 %v2, i32* %res) {
entry:
; CHECK-LABEL: uaddo.i32
; CHECK: adds w8, w0, w1
; CHECK-NEXT: csinc w0, wzr, wzr, lo
; CHECK-NEXT: cset w0, hs
%t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 %v2)
%val = extractvalue {i32, i1} %t, 0
%obit = extractvalue {i32, i1} %t, 1
@ -43,7 +43,7 @@ define i1 @uaddo.i64(i64 %v1, i64 %v2, i64* %res) {
entry:
; CHECK-LABEL: uaddo.i64
; CHECK: adds x8, x0, x1
; CHECK-NEXT: csinc w0, wzr, wzr, lo
; CHECK-NEXT: cset w0, hs
%t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 %v2)
%val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1
@ -55,7 +55,7 @@ define i1 @ssubo.i32(i32 %v1, i32 %v2, i32* %res) {
entry:
; CHECK-LABEL: ssubo.i32
; CHECK: subs w8, w0, w1
; CHECK-NEXT: csinc w0, wzr, wzr, vc
; CHECK-NEXT: cset w0, vs
%t = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %v1, i32 %v2)
%val = extractvalue {i32, i1} %t, 0
%obit = extractvalue {i32, i1} %t, 1
@ -67,7 +67,7 @@ define i1 @ssubo.i64(i64 %v1, i64 %v2, i64* %res) {
entry:
; CHECK-LABEL: ssubo.i64
; CHECK: subs x8, x0, x1
; CHECK-NEXT: csinc w0, wzr, wzr, vc
; CHECK-NEXT: cset w0, vs
%t = call {i64, i1} @llvm.ssub.with.overflow.i64(i64 %v1, i64 %v2)
%val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1
@ -79,7 +79,7 @@ define i1 @usubo.i32(i32 %v1, i32 %v2, i32* %res) {
entry:
; CHECK-LABEL: usubo.i32
; CHECK: subs w8, w0, w1
; CHECK-NEXT: csinc w0, wzr, wzr, hs
; CHECK-NEXT: cset w0, lo
%t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %v1, i32 %v2)
%val = extractvalue {i32, i1} %t, 0
%obit = extractvalue {i32, i1} %t, 1
@ -91,7 +91,7 @@ define i1 @usubo.i64(i64 %v1, i64 %v2, i64* %res) {
entry:
; CHECK-LABEL: usubo.i64
; CHECK: subs x8, x0, x1
; CHECK-NEXT: csinc w0, wzr, wzr, hs
; CHECK-NEXT: cset w0, lo
%t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %v1, i64 %v2)
%val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1
@ -105,7 +105,7 @@ entry:
; CHECK: smull x8, w0, w1
; CHECK-NEXT: lsr x9, x8, #32
; CHECK-NEXT: cmp w9, w8, asr #31
; CHECK-NEXT: csinc w0, wzr, wzr, eq
; CHECK-NEXT: cset w0, ne
%t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %v1, i32 %v2)
%val = extractvalue {i32, i1} %t, 0
%obit = extractvalue {i32, i1} %t, 1
@ -119,7 +119,7 @@ entry:
; CHECK: mul x8, x0, x1
; CHECK-NEXT: smulh x9, x0, x1
; CHECK-NEXT: cmp x9, x8, asr #63
; CHECK-NEXT: csinc w0, wzr, wzr, eq
; CHECK-NEXT: cset w0, ne
%t = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %v1, i64 %v2)
%val = extractvalue {i64, i1} %t, 0
%obit = extractvalue {i64, i1} %t, 1
@ -132,7 +132,7 @@ entry:
; CHECK-LABEL: umulo.i32
; CHECK: umull x8, w0, w1
; CHECK-NEXT: cmp xzr, x8, lsr #32
; CHECK-NEXT: csinc w0, wzr, wzr, eq
; CHECK-NEXT: cset w0, ne
%t = call {i32, i1} @llvm.umul.with.overflow.i32(i32 %v1, i32 %v2)
%val = extractvalue {i32, i1} %t, 0
%obit = extractvalue {i32, i1} %t, 1
@ -145,7 +145,7 @@ entry:
; CHECK-LABEL: umulo.i64
; CHECK: umulh x8, x0, x1
; CHECK-NEXT: cmp xzr, x8
; CHECK-NEXT: csinc w8, wzr, wzr, eq
; CHECK-NEXT: cset w8, ne
; CHECK-NEXT: mul x9, x0, x1
%t = call {i64, i1} @llvm.umul.with.overflow.i64(i64 %v1, i64 %v2)
%val = extractvalue {i64, i1} %t, 0

8
test/CodeGen/X86/divide-by-constant.ll
View File

@ -7,7 +7,7 @@ entry:
%div = udiv i16 %x, 33
ret i16 %div
; CHECK-LABEL: test1:
; CHECK: imull $63551, %eax, %eax
; CHECK: imull $63551, %eax
; CHECK-NEXT: shrl $21, %eax
; CHECK-NEXT: ret
}
@ -18,7 +18,7 @@ entry:
ret i16 %div
; CHECK-LABEL: test2:
; CHECK: imull $43691, %eax, %eax
; CHECK: imull $43691, %eax
; CHECK-NEXT: shrl $17, %eax
; CHECK-NEXT: ret
}
@ -30,7 +30,7 @@ entry:
; CHECK-LABEL: test3:
; CHECK: movzbl 8(%esp), %eax
; CHECK-NEXT: imull $171, %eax, %eax
; CHECK-NEXT: imull $171, %eax
; CHECK-NEXT: shrl $9, %eax
; CHECK-NEXT: ret
}
@ -40,7 +40,7 @@ entry:
%div = sdiv i16 %x, 33 ; <i32> [#uses=1]
ret i16 %div
; CHECK-LABEL: test4:
; CHECK: imull $1986, %eax, %
; CHECK: imull $1986, %eax
}
define i32 @test5(i32 %A) nounwind {

162
test/MC/AArch64/basic-a64-instructions.s
View File

@ -731,23 +731,34 @@ _func:
neg w26, w25, lsl #29
neg w24, w23, lsl #31
// CHECK-AARCH64: sub w28, wzr, w27 // encoding: [0xfc,0x03,0x1b,0x4b]
// CHECK-AARCH64: neg w26, w25, lsl #29 // encoding: [0xfa,0x77,0x19,0x4b]
// CHECK-AARCH64: neg w24, w23, lsl #31 // encoding: [0xf8,0x7f,0x17,0x4b]
// CHECK-ARM64: neg w28, w27 // encoding: [0xfc,0x03,0x1b,0x4b]
// CHECK: sub w26, wzr, w25, lsl #29 // encoding: [0xfa,0x77,0x19,0x4b]
// CHECK: sub w24, wzr, w23, lsl #31 // encoding: [0xf8,0x7f,0x17,0x4b]
// CHECK-ARM64: sub w26, wzr, w25, lsl #29 // encoding: [0xfa,0x77,0x19,0x4b]
// CHECK-ARM64: sub w24, wzr, w23, lsl #31 // encoding: [0xf8,0x7f,0x17,0x4b]
neg w22, w21, lsr #0
neg w20, w19, lsr #1
neg w18, w17, lsr #31
// CHECK: sub w22, wzr, w21, lsr #0 // encoding: [0xf6,0x03,0x55,0x4b]
// CHECK: sub w20, wzr, w19, lsr #1 // encoding: [0xf4,0x07,0x53,0x4b]
// CHECK: sub w18, wzr, w17, lsr #31 // encoding: [0xf2,0x7f,0x51,0x4b]
// CHECK-AARCH64: neg w22, w21, lsr #0 // encoding: [0xf6,0x03,0x55,0x4b]
// CHECK-AARCH64: neg w20, w19, lsr #1 // encoding: [0xf4,0x07,0x53,0x4b]
// CHECK-AARCH64: neg w18, w17, lsr #31 // encoding: [0xf2,0x7f,0x51,0x4b]
// CHECK-ARM64: sub w22, wzr, w21, lsr #0 // encoding: [0xf6,0x03,0x55,0x4b]
// CHECK-ARM64: sub w20, wzr, w19, lsr #1 // encoding: [0xf4,0x07,0x53,0x4b]
// CHECK-ARM64: sub w18, wzr, w17, lsr #31 // encoding: [0xf2,0x7f,0x51,0x4b]
neg w16, w15, asr #0
neg w14, w13, asr #12
neg w12, w11, asr #31
// CHECK: sub w16, wzr, w15, asr #0 // encoding: [0xf0,0x03,0x8f,0x4b]
// CHECK: sub w14, wzr, w13, asr #12 // encoding: [0xee,0x33,0x8d,0x4b]
// CHECK: sub w12, wzr, w11, asr #31 // encoding: [0xec,0x7f,0x8b,0x4b]
// CHECK-AARCH64: neg w16, w15, asr #0 // encoding: [0xf0,0x03,0x8f,0x4b]
// CHECK-AARCH64: neg w14, w13, asr #12 // encoding: [0xee,0x33,0x8d,0x4b]
// CHECK-AARCH64: neg w12, w11, asr #31 // encoding: [0xec,0x7f,0x8b,0x4b]
// CHECK-ARM64: sub w16, wzr, w15, asr #0 // encoding: [0xf0,0x03,0x8f,0x4b]
// CHECK-ARM64: sub w14, wzr, w13, asr #12 // encoding: [0xee,0x33,0x8d,0x4b]
// CHECK-ARM64: sub w12, wzr, w11, asr #31 // encoding: [0xec,0x7f,0x8b,0x4b]
neg x29, x30
neg x30, xzr
@ -763,23 +774,34 @@ _func:
neg x26, x25, lsl #29
neg x24, x23, lsl #31
// CHECK-AARCH64: sub x28, xzr, x27 // encoding: [0xfc,0x03,0x1b,0xcb]
// CHECK-AARCH64: neg x26, x25, lsl #29 // encoding: [0xfa,0x77,0x19,0xcb]
// CHECK-AARCH64: neg x24, x23, lsl #31 // encoding: [0xf8,0x7f,0x17,0xcb]
// CHECK-ARM64: neg x28, x27 // encoding: [0xfc,0x03,0x1b,0xcb]
// CHECK: sub x26, xzr, x25, lsl #29 // encoding: [0xfa,0x77,0x19,0xcb]
// CHECK: sub x24, xzr, x23, lsl #31 // encoding: [0xf8,0x7f,0x17,0xcb]
// CHECK-ARM64: sub x26, xzr, x25, lsl #29 // encoding: [0xfa,0x77,0x19,0xcb]
// CHECK-ARM64: sub x24, xzr, x23, lsl #31 // encoding: [0xf8,0x7f,0x17,0xcb]
neg x22, x21, lsr #0
neg x20, x19, lsr #1
neg x18, x17, lsr #31
// CHECK: sub x22, xzr, x21, lsr #0 // encoding: [0xf6,0x03,0x55,0xcb]
// CHECK: sub x20, xzr, x19, lsr #1 // encoding: [0xf4,0x07,0x53,0xcb]
// CHECK: sub x18, xzr, x17, lsr #31 // encoding: [0xf2,0x7f,0x51,0xcb]
// CHECK-AARCH64: neg x22, x21, lsr #0 // encoding: [0xf6,0x03,0x55,0xcb]
// CHECK-AARCH64: neg x20, x19, lsr #1 // encoding: [0xf4,0x07,0x53,0xcb]
// CHECK-AARCH64: neg x18, x17, lsr #31 // encoding: [0xf2,0x7f,0x51,0xcb]
// CHECK-ARM64: sub x22, xzr, x21, lsr #0 // encoding: [0xf6,0x03,0x55,0xcb]
// CHECK-ARM64: sub x20, xzr, x19, lsr #1 // encoding: [0xf4,0x07,0x53,0xcb]
// CHECK-ARM64: sub x18, xzr, x17, lsr #31 // encoding: [0xf2,0x7f,0x51,0xcb]
neg x16, x15, asr #0
neg x14, x13, asr #12
neg x12, x11, asr #31
// CHECK: sub x16, xzr, x15, asr #0 // encoding: [0xf0,0x03,0x8f,0xcb]
// CHECK: sub x14, xzr, x13, asr #12 // encoding: [0xee,0x33,0x8d,0xcb]
// CHECK: sub x12, xzr, x11, asr #31 // encoding: [0xec,0x7f,0x8b,0xcb]
// CHECK-AARCH64: neg x16, x15, asr #0 // encoding: [0xf0,0x03,0x8f,0xcb]
// CHECK-AARCH64: neg x14, x13, asr #12 // encoding: [0xee,0x33,0x8d,0xcb]
// CHECK-AARCH64: neg x12, x11, asr #31 // encoding: [0xec,0x7f,0x8b,0xcb]
// CHECK-ARM64: sub x16, xzr, x15, asr #0 // encoding: [0xf0,0x03,0x8f,0xcb]
// CHECK-ARM64: sub x14, xzr, x13, asr #12 // encoding: [0xee,0x33,0x8d,0xcb]
// CHECK-ARM64: sub x12, xzr, x11, asr #31 // encoding: [0xec,0x7f,0x8b,0xcb]
negs w29, w30
negs w30, wzr
@ -795,23 +817,34 @@ _func:
negs w26, w25, lsl #29
negs w24, w23, lsl #31
// CHECK-AARCH64: subs w28, wzr, w27 // encoding: [0xfc,0x03,0x1b,0x6b]
// CHECK-AARCH64: negs w26, w25, lsl #29 // encoding: [0xfa,0x77,0x19,0x6b]
// CHECK-AARCH64: negs w24, w23, lsl #31 // encoding: [0xf8,0x7f,0x17,0x6b]
// CHECK-ARM64: negs w28, w27 // encoding: [0xfc,0x03,0x1b,0x6b]
// CHECK: subs w26, wzr, w25, lsl #29 // encoding: [0xfa,0x77,0x19,0x6b]
// CHECK: subs w24, wzr, w23, lsl #31 // encoding: [0xf8,0x7f,0x17,0x6b]
// CHECK-ARM64: subs w26, wzr, w25, lsl #29 // encoding: [0xfa,0x77,0x19,0x6b]
// CHECK-ARM64: subs w24, wzr, w23, lsl #31 // encoding: [0xf8,0x7f,0x17,0x6b]
negs w22, w21, lsr #0
negs w20, w19, lsr #1
negs w18, w17, lsr #31
// CHECK: subs w22, wzr, w21, lsr #0 // encoding: [0xf6,0x03,0x55,0x6b]
// CHECK: subs w20, wzr, w19, lsr #1 // encoding: [0xf4,0x07,0x53,0x6b]
// CHECK: subs w18, wzr, w17, lsr #31 // encoding: [0xf2,0x7f,0x51,0x6b]
// CHECK-AARCH64: negs w22, w21, lsr #0 // encoding: [0xf6,0x03,0x55,0x6b]
// CHECK-AARCH64: negs w20, w19, lsr #1 // encoding: [0xf4,0x07,0x53,0x6b]
// CHECK-AARCH64: negs w18, w17, lsr #31 // encoding: [0xf2,0x7f,0x51,0x6b]
// CHECK-ARM64: subs w22, wzr, w21, lsr #0 // encoding: [0xf6,0x03,0x55,0x6b]
// CHECK-ARM64: subs w20, wzr, w19, lsr #1 // encoding: [0xf4,0x07,0x53,0x6b]
// CHECK-ARM64: subs w18, wzr, w17, lsr #31 // encoding: [0xf2,0x7f,0x51,0x6b]
negs w16, w15, asr #0
negs w14, w13, asr #12
negs w12, w11, asr #31
// CHECK: subs w16, wzr, w15, asr #0 // encoding: [0xf0,0x03,0x8f,0x6b]
// CHECK: subs w14, wzr, w13, asr #12 // encoding: [0xee,0x33,0x8d,0x6b]
// CHECK: subs w12, wzr, w11, asr #31 // encoding: [0xec,0x7f,0x8b,0x6b]
// CHECK-AARCH64: negs w16, w15, asr #0 // encoding: [0xf0,0x03,0x8f,0x6b]
// CHECK-AARCH64: negs w14, w13, asr #12 // encoding: [0xee,0x33,0x8d,0x6b]
// CHECK-AARCH64: negs w12, w11, asr #31 // encoding: [0xec,0x7f,0x8b,0x6b]
// CHECK-ARM64: subs w16, wzr, w15, asr #0 // encoding: [0xf0,0x03,0x8f,0x6b]
// CHECK-ARM64: subs w14, wzr, w13, asr #12 // encoding: [0xee,0x33,0x8d,0x6b]
// CHECK-ARM64: subs w12, wzr, w11, asr #31 // encoding: [0xec,0x7f,0x8b,0x6b]
negs x29, x30
negs x30, xzr
@ -827,23 +860,34 @@ _func:
negs x26, x25, lsl #29
negs x24, x23, lsl #31
// CHECK-AARCH64: subs x28, xzr, x27 // encoding: [0xfc,0x03,0x1b,0xeb]
// CHECK-AARCH64: negs x26, x25, lsl #29 // encoding: [0xfa,0x77,0x19,0xeb]
// CHECK-AARCH64: negs x24, x23, lsl #31 // encoding: [0xf8,0x7f,0x17,0xeb]
// CHECK-ARM64: negs x28, x27 // encoding: [0xfc,0x03,0x1b,0xeb]
// CHECK: subs x26, xzr, x25, lsl #29 // encoding: [0xfa,0x77,0x19,0xeb]
// CHECK: subs x24, xzr, x23, lsl #31 // encoding: [0xf8,0x7f,0x17,0xeb]
// CHECK-ARM64: subs x26, xzr, x25, lsl #29 // encoding: [0xfa,0x77,0x19,0xeb]
// CHECK-ARM64: subs x24, xzr, x23, lsl #31 // encoding: [0xf8,0x7f,0x17,0xeb]
negs x22, x21, lsr #0
negs x20, x19, lsr #1
negs x18, x17, lsr #31
// CHECK: subs x22, xzr, x21, lsr #0 // encoding: [0xf6,0x03,0x55,0xeb]
// CHECK: subs x20, xzr, x19, lsr #1 // encoding: [0xf4,0x07,0x53,0xeb]
// CHECK: subs x18, xzr, x17, lsr #31 // encoding: [0xf2,0x7f,0x51,0xeb]
// CHECK-AARCH64: negs x22, x21, lsr #0 // encoding: [0xf6,0x03,0x55,0xeb]
// CHECK-AARCH64: negs x20, x19, lsr #1 // encoding: [0xf4,0x07,0x53,0xeb]
// CHECK-AARCH64: negs x18, x17, lsr #31 // encoding: [0xf2,0x7f,0x51,0xeb]
// CHECK-ARM64: subs x22, xzr, x21, lsr #0 // encoding: [0xf6,0x03,0x55,0xeb]
// CHECK-ARM64: subs x20, xzr, x19, lsr #1 // encoding: [0xf4,0x07,0x53,0xeb]
// CHECK-ARM64: subs x18, xzr, x17, lsr #31 // encoding: [0xf2,0x7f,0x51,0xeb]
negs x16, x15, asr #0
negs x14, x13, asr #12
negs x12, x11, asr #31
// CHECK: subs x16, xzr, x15, asr #0 // encoding: [0xf0,0x03,0x8f,0xeb]
// CHECK: subs x14, xzr, x13, asr #12 // encoding: [0xee,0x33,0x8d,0xeb]
// CHECK: subs x12, xzr, x11, asr #31 // encoding: [0xec,0x7f,0x8b,0xeb]
// CHECK-AARCH64: negs x16, x15, asr #0 // encoding: [0xf0,0x03,0x8f,0xeb]
// CHECK-AARCH64: negs x14, x13, asr #12 // encoding: [0xee,0x33,0x8d,0xeb]
// CHECK-AARCH64: negs x12, x11, asr #31 // encoding: [0xec,0x7f,0x8b,0xeb]
// CHECK-ARM64: subs x16, xzr, x15, asr #0 // encoding: [0xf0,0x03,0x8f,0xeb]
// CHECK-ARM64: subs x14, xzr, x13, asr #12 // encoding: [0xee,0x33,0x8d,0xeb]
// CHECK-ARM64: subs x12, xzr, x11, asr #31 // encoding: [0xec,0x7f,0x8b,0xeb]
//------------------------------------------------------------------------------
// Add-sub (shifted register)
@ -1513,55 +1557,55 @@ _func:
cset w3, eq
cset x9, pl
// CHECK: csinc w3, wzr, wzr, ne // encoding: [0xe3,0x17,0x9f,0x1a]
// CHECK: csinc x9, xzr, xzr, mi // encoding: [0xe9,0x47,0x9f,0x9a]
// CHECK: cset w3, eq // encoding: [0xe3,0x17,0x9f,0x1a]
// CHECK: cset x9, pl // encoding: [0xe9,0x47,0x9f,0x9a]
csetm w20, ne
csetm x30, ge
// CHECK: csinv w20, wzr, wzr, eq // encoding: [0xf4,0x03,0x9f,0x5a]
// CHECK: csinv x30, xzr, xzr, lt // encoding: [0xfe,0xb3,0x9f,0xda]
// CHECK: csetm w20, ne // encoding: [0xf4,0x03,0x9f,0x5a]
// CHECK: csetm x30, ge // encoding: [0xfe,0xb3,0x9f,0xda]
cinc w3, w5, gt
cinc wzr, w4, le
cinc w9, wzr, lt
// CHECK: csinc w3, w5, w5, le // encoding: [0xa3,0xd4,0x85,0x1a]
// CHECK: csinc wzr, w4, w4, gt // encoding: [0x9f,0xc4,0x84,0x1a]
// CHECK: csinc w9, wzr, wzr, ge // encoding: [0xe9,0xa7,0x9f,0x1a]
// CHECK: cinc w3, w5, gt // encoding: [0xa3,0xd4,0x85,0x1a]
// CHECK: cinc wzr, w4, le // encoding: [0x9f,0xc4,0x84,0x1a]
// CHECK: cset w9, lt // encoding: [0xe9,0xa7,0x9f,0x1a]
cinc x3, x5, gt
cinc xzr, x4, le
cinc x9, xzr, lt
// CHECK: csinc x3, x5, x5, le // encoding: [0xa3,0xd4,0x85,0x9a]
// CHECK: csinc xzr, x4, x4, gt // encoding: [0x9f,0xc4,0x84,0x9a]
// CHECK: csinc x9, xzr, xzr, ge // encoding: [0xe9,0xa7,0x9f,0x9a]
// CHECK: cinc x3, x5, gt // encoding: [0xa3,0xd4,0x85,0x9a]
// CHECK: cinc xzr, x4, le // encoding: [0x9f,0xc4,0x84,0x9a]
// CHECK: cset x9, lt // encoding: [0xe9,0xa7,0x9f,0x9a]
cinv w3, w5, gt
cinv wzr, w4, le
cinv w9, wzr, lt
// CHECK: csinv w3, w5, w5, le // encoding: [0xa3,0xd0,0x85,0x5a]
// CHECK: csinv wzr, w4, w4, gt // encoding: [0x9f,0xc0,0x84,0x5a]
// CHECK: csinv w9, wzr, wzr, ge // encoding: [0xe9,0xa3,0x9f,0x5a]
// CHECK: cinv w3, w5, gt // encoding: [0xa3,0xd0,0x85,0x5a]
// CHECK: cinv wzr, w4, le // encoding: [0x9f,0xc0,0x84,0x5a]
// CHECK: csetm w9, lt // encoding: [0xe9,0xa3,0x9f,0x5a]
cinv x3, x5, gt
cinv xzr, x4, le
cinv x9, xzr, lt
// CHECK: csinv x3, x5, x5, le // encoding: [0xa3,0xd0,0x85,0xda]
// CHECK: csinv xzr, x4, x4, gt // encoding: [0x9f,0xc0,0x84,0xda]
// CHECK: csinv x9, xzr, xzr, ge // encoding: [0xe9,0xa3,0x9f,0xda]
// CHECK: cinv x3, x5, gt // encoding: [0xa3,0xd0,0x85,0xda]
// CHECK: cinv xzr, x4, le // encoding: [0x9f,0xc0,0x84,0xda]
// CHECK: csetm x9, lt // encoding: [0xe9,0xa3,0x9f,0xda]
cneg w3, w5, gt
cneg wzr, w4, le
cneg w9, wzr, lt
// CHECK: csneg w3, w5, w5, le // encoding: [0xa3,0xd4,0x85,0x5a]
// CHECK: csneg wzr, w4, w4, gt // encoding: [0x9f,0xc4,0x84,0x5a]
// CHECK: csneg w9, wzr, wzr, ge // encoding: [0xe9,0xa7,0x9f,0x5a]
// CHECK: cneg w3, w5, gt // encoding: [0xa3,0xd4,0x85,0x5a]
// CHECK: cneg wzr, w4, le // encoding: [0x9f,0xc4,0x84,0x5a]
// CHECK: cneg w9, wzr, lt // encoding: [0xe9,0xa7,0x9f,0x5a]
cneg x3, x5, gt
cneg xzr, x4, le
cneg x9, xzr, lt
// CHECK: csneg x3, x5, x5, le // encoding: [0xa3,0xd4,0x85,0xda]
// CHECK: csneg xzr, x4, x4, gt // encoding: [0x9f,0xc4,0x84,0xda]
// CHECK: csneg x9, xzr, xzr, ge // encoding: [0xe9,0xa7,0x9f,0xda]
// CHECK: cneg x3, x5, gt // encoding: [0xa3,0xd4,0x85,0xda]
// CHECK: cneg xzr, x4, le // encoding: [0x9f,0xc4,0x84,0xda]
// CHECK: cneg x9, xzr, lt // encoding: [0xe9,0xa7,0x9f,0xda]
//------------------------------------------------------------------------------
// Data-processing (1 source)
@ -1859,11 +1903,11 @@ _func:
ror x19, x23, #24
ror x29, xzr, #63
// CHECK: extr x19, x23, x23, #24 // encoding: [0xf3,0x62,0xd7,0x93]
// CHECK: extr x29, xzr, xzr, #63 // encoding: [0xfd,0xff,0xdf,0x93]
// CHECK: ror x19, x23, #24 // encoding: [0xf3,0x62,0xd7,0x93]
// CHECK: ror x29, xzr, #63 // encoding: [0xfd,0xff,0xdf,0x93]
ror w9, w13, #31
// CHECK: extr w9, w13, w13, #31 // encoding: [0xa9,0x7d,0x8d,0x13]
// CHECK: ror w9, w13, #31 // encoding: [0xa9,0x7d,0x8d,0x13]
//------------------------------------------------------------------------------
// Floating-point compare
@ -3406,7 +3450,7 @@ _func:
mov w3, #0xf000f
mov x10, #0xaaaaaaaaaaaaaaaa
// CHECK: orr w3, wzr, #0xf000f // encoding: [0xe3,0x8f,0x00,0x32]
// CHECK: orr x10, xzr, #0xaaaaaaaaaaaaaaaa // encoding: [0xea,0xf3,0x01,0xb2]
// CHECK: orr x10, xzr, #0xaaaaaaaaaaaaaaaa // encoding: [0xea,0xf3,0x01,0xb2]
//------------------------------------------------------------------------------
// Logical (shifted register)
@ -3747,7 +3791,7 @@ _func:
sys #7, c5, c9, #7, x5
sys #0, c15, c15, #2
// CHECK: sys #7, c5, c9, #7, x5 // encoding: [0xe5,0x59,0x0f,0xd5]
// CHECK: sys #0, c15, c15, #2, xzr // encoding: [0x5f,0xff,0x08,0xd5]
// CHECK: sys #0, c15, c15, #2 // encoding: [0x5f,0xff,0x08,0xd5]
sysl x9, #7, c5, c9, #7
sysl x1, #0, c15, c15, #2

20
test/MC/ARM64/aliases.s
View File

@ -218,8 +218,8 @@ foo:
ubfm x0, x0, #63, #62
ubfm w0, w0, #4, #31
ubfm x0, x0, #4, #63
; CHECK: extr w1, w3, w3, #5
; CHECK: extr x1, x3, x3, #5
; CHECK: ror w1, w3, #5
; CHECK: ror x1, x3, #5
ror w1, w3, #5
ror x1, x3, #5
; CHECK: lsl w1, wzr, #3
@ -302,14 +302,14 @@ foo:
cinv w1, w2, mi
cinv x1, x2, mi
; CHECK: csinc w1, wzr, wzr, ne
; CHECK: csinc x1, xzr, xzr, ne
; CHECK: csinv w1, wzr, wzr, eq
; CHECK: csinv x1, xzr, xzr, eq
; CHECK: csinc w1, w2, w2, ge
; CHECK: csinc x1, x2, x2, ge
; CHECK: csinv w1, w2, w2, pl
; CHECK: csinv x1, x2, x2, pl
; CHECK: cset w1, eq
; CHECK: cset x1, eq
; CHECK: csetm w1, ne
; CHECK: csetm x1, ne
; CHECK: cinc w1, w2, lt
; CHECK: cinc x1, x2, lt
; CHECK: cinv w1, w2, mi
; CHECK: cinv x1, x2, mi
;-----------------------------------------------------------------------------
; SYS aliases

56
test/MC/Disassembler/AArch64/basic-a64-instructions.txt
View File

@ -941,21 +941,21 @@
0xe5 0x27 0x86 0xda
0x7 0x35 0x9f 0xda
# CHECK: csinc w3, wzr, wzr, ne
# CHECK: csinc x9, xzr, xzr, mi
# CHECK: csinv w20, wzr, wzr, eq
# CHECK: csinv x30, xzr, xzr, lt
# CHECK: cset w3, eq
# CHECK: cset x9, pl
# CHECK: csetm w20, ne
# CHECK: csetm x30, ge
0xe3 0x17 0x9f 0x1a
0xe9 0x47 0x9f 0x9a
0xf4 0x3 0x9f 0x5a
0xfe 0xb3 0x9f 0xda
# CHECK: csinc w3, w5, w5, le
# CHECK: csinc wzr, w4, w4, gt
# CHECK: csinc w9, wzr, wzr, ge
# CHECK: csinc x3, x5, x5, le
# CHECK: csinc xzr, x4, x4, gt
# CHECK: csinc x9, xzr, xzr, ge
# CHECK: cinc w3, w5, gt
# CHECK: cinc wzr, w4, le
# CHECK: cset w9, lt
# CHECK: cinc x3, x5, gt
# CHECK: cinc xzr, x4, le
# CHECK: cset x9, lt
0xa3 0xd4 0x85 0x1a
0x9f 0xc4 0x84 0x1a
0xe9 0xa7 0x9f 0x1a
@ -963,12 +963,12 @@
0x9f 0xc4 0x84 0x9a
0xe9 0xa7 0x9f 0x9a
# CHECK: csinv w3, w5, w5, le
# CHECK: csinv wzr, w4, w4, gt
# CHECK: csinv w9, wzr, wzr, ge
# CHECK: csinv x3, x5, x5, le
# CHECK: csinv xzr, x4, x4, gt
# CHECK: csinv x9, xzr, xzr, ge
# CHECK: cinv w3, w5, gt
# CHECK: cinv wzr, w4, le
# CHECK: csetm w9, lt
# CHECK: cinv x3, x5, gt
# CHECK: cinv xzr, x4, le
# CHECK: csetm x9, lt
0xa3 0xd0 0x85 0x5a
0x9f 0xc0 0x84 0x5a
0xe9 0xa3 0x9f 0x5a
@ -976,12 +976,12 @@
0x9f 0xc0 0x84 0xda
0xe9 0xa3 0x9f 0xda
# CHECK: csneg w3, w5, w5, le
# CHECK: csneg wzr, w4, w4, gt
# CHECK: csneg w9, wzr, wzr, ge
# CHECK: csneg x3, x5, x5, le
# CHECK: csneg xzr, x4, x4, gt
# CHECK: csneg x9, xzr, xzr, ge
# CHECK: cneg w3, w5, gt
# CHECK: cneg wzr, w4, le
# CHECK: cneg w9, wzr, lt
# CHECK: cneg x3, x5, gt
# CHECK: cneg xzr, x4, le
# CHECK: cneg x9, xzr, lt
0xa3 0xd4 0x85 0x5a
0x9f 0xc4 0x84 0x5a
0xe9 0xa7 0x9f 0x5a
@ -1285,9 +1285,9 @@
0xa3 0x3c 0xc7 0x93
0xab 0xfd 0xd1 0x93
# CHECK: extr x19, x23, x23, #24
# CHECK: extr x29, xzr, xzr, #63
# CHECK: extr w9, w13, w13, #31
# CHECK: ror x19, x23, #24
# CHECK: ror x29, xzr, #63
# CHECK: ror w9, w13, #31
0xf3 0x62 0xd7 0x93
0xfd 0xff 0xdf 0x93
0xa9 0x7d 0x8d 0x13
@ -3015,15 +3015,15 @@
0xe9 0x59 0x2f 0xd5
0x41 0xff 0x28 0xd5
# CHECK: {{sys #0, c7, c1, #0, xzr|ic ialluis}}
# CHECK: {{sys #0, c7, c5, #0, xzr|ic iallu}}
# CHECK: {{sys #0, c7, c1, #0|ic ialluis}}
# CHECK: {{sys #0, c7, c5, #0|ic iallu}}
# CHECK: {{sys #3, c7, c5, #1|ic ivau}}, x9
0x1f 0x71 0x8 0xd5
0x1f 0x75 0x8 0xd5
0x29 0x75 0xb 0xd5
# CHECK: {{sys #3, c7, c4, #1|dc zva}}, x12
# CHECK: {{sys #0, c7, c6, #1|dc ivac}}, xzr
# CHECK: {{sys #0, c7, c6, #1|dc ivac}}
# CHECK: {{sys #0, c7, c6, #2|dc isw}}, x2
# CHECK: {{sys #3, c7, c10, #1|dc cvac}}, x9
# CHECK: {{sys #0, c7, c10, #2|dc csw}}, x10

4
test/MC/Mips/micromips-control-instructions.s
View File

@ -10,7 +10,7 @@
# Little endian
#------------------------------------------------------------------------------
# CHECK-EL: break # encoding: [0x00,0x00,0x07,0x00]
# CHECK-EL: break 7, 0 # encoding: [0x07,0x00,0x07,0x00]
# CHECK-EL: break 7 # encoding: [0x07,0x00,0x07,0x00]
# CHECK-EL: break 7, 5 # encoding: [0x07,0x00,0x47,0x01]
# CHECK-EL: syscall # encoding: [0x00,0x00,0x7c,0x8b]
# CHECK-EL: syscall 396 # encoding: [0x8c,0x01,0x7c,0x8b]
@ -28,7 +28,7 @@
# Big endian
#------------------------------------------------------------------------------
# CHECK-EB: break # encoding: [0x00,0x00,0x00,0x07]
# CHECK-EB: break 7, 0 # encoding: [0x00,0x07,0x00,0x07]
# CHECK-EB: break 7 # encoding: [0x00,0x07,0x00,0x07]
# CHECK-EB: break 7, 5 # encoding: [0x00,0x07,0x01,0x47]
# CHECK-EB: syscall # encoding: [0x00,0x00,0x8b,0x7c]
# CHECK-EB: syscall 396 # encoding: [0x01,0x8c,0x8b,0x7c]

4
test/MC/Mips/mips-control-instructions.s
View File

@ -4,7 +4,7 @@
# RUN: | FileCheck -check-prefix=CHECK64 %s
# CHECK32: break # encoding: [0x00,0x00,0x00,0x0d]
# CHECK32: break 7, 0 # encoding: [0x00,0x07,0x00,0x0d]
# CHECK32: break 7 # encoding: [0x00,0x07,0x00,0x0d]
# CHECK32: break 7, 5 # encoding: [0x00,0x07,0x01,0x4d]
# CHECK32: syscall # encoding: [0x00,0x00,0x00,0x0c]
# CHECK32: syscall 13396 # encoding: [0x00,0x0d,0x15,0x0c]
@ -37,7 +37,7 @@
# CHECK32: tnei $3, 1023 # encoding: [0x04,0x6e,0x03,0xff]
# CHECK64: break # encoding: [0x00,0x00,0x00,0x0d]
# CHECK64: break 7, 0 # encoding: [0x00,0x07,0x00,0x0d]
# CHECK64: break 7 # encoding: [0x00,0x07,0x00,0x0d]
# CHECK64: break 7, 5 # encoding: [0x00,0x07,0x01,0x4d]
# CHECK64: syscall # encoding: [0x00,0x00,0x00,0x0c]
# CHECK64: syscall 13396 # encoding: [0x00,0x0d,0x15,0x0c]

2
test/MC/X86/x86-64.s
View File

@ -203,7 +203,7 @@ int $3
// CHECK-STDERR: warning: scale factor without index register is ignored
movaps %xmm3, (%esi, 2)
// CHECK: imull $12, %eax, %eax
// CHECK: imull $12, %eax
imul $12, %eax
// CHECK: imull %ecx, %eax

95
utils/TableGen/AsmWriterEmitter.cpp
View File

@ -39,6 +39,7 @@ class AsmWriterEmitter {
std::map<const CodeGenInstruction*, AsmWriterInst*> CGIAWIMap;
const std::vector<const CodeGenInstruction*> *NumberedInstructions;
std::vector<AsmWriterInst> Instructions;
std::vector<std::string> PrintMethods;
public:
AsmWriterEmitter(RecordKeeper &R);
@ -629,22 +630,25 @@ namespace {
// alias for that pattern.
class IAPrinter {
std::vector<std::string> Conds;
std::map<StringRef, unsigned> OpMap;
std::map<StringRef, std::pair<int, int>> OpMap;
SmallVector<Record*, 4> ReqFeatures;
std::string Result;
std::string AsmString;
SmallVector<Record*, 4> ReqFeatures;
public:
IAPrinter(std::string R, std::string AS)
: Result(R), AsmString(AS) {}
IAPrinter(std::string R, std::string AS) : Result(R), AsmString(AS) {}
void addCond(const std::string &C) { Conds.push_back(C); }
void addOperand(StringRef Op, unsigned Idx) {
assert(Idx < 0xFF && "Index too large!");
OpMap[Op] = Idx;
void addOperand(StringRef Op, int OpIdx, int PrintMethodIdx = -1) {
assert(OpIdx >= 0 && OpIdx < 0xFE && "Idx out of range");
assert(PrintMethodIdx == -1 || PrintMethodIdx < 0xFF && "Idx out of range");
OpMap[Op] = std::make_pair(OpIdx, PrintMethodIdx);
}
unsigned getOpIndex(StringRef Op) { return OpMap[Op]; }
bool isOpMapped(StringRef Op) { return OpMap.find(Op) != OpMap.end(); }
int getOpIndex(StringRef Op) { return OpMap[Op].first; }
std::pair<int, int> &getOpData(StringRef Op) { return OpMap[Op]; }
void print(raw_ostream &O) {
if (Conds.empty() && ReqFeatures.empty()) {
@ -686,7 +690,16 @@ public:
++I;
StringRef Name(Start, I - Start);
assert(isOpMapped(Name) && "Unmapped operand!");
OS << format("\\x%02X", (unsigned char)getOpIndex(Name) + 1);
int OpIndex, PrintIndex;
std::tie(OpIndex, PrintIndex) = getOpData(Name);
if (PrintIndex == -1) {
// Can use the default printOperand route.
OS << format("\\x%02X", (unsigned char)OpIndex + 1);
} else
// 3 bytes if a PrintMethod is needed: 0xFF, the MCInst operand
// number, and which of our pre-detected Methods to call.
OS << format("\\xFF\\x%02X\\x%02X", OpIndex + 1, PrintIndex + 1);
} else {
++I;
}
@ -755,6 +768,10 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) {
O << "\n#ifdef PRINT_ALIAS_INSTR\n";
O << "#undef PRINT_ALIAS_INSTR\n\n";
//////////////////////////////
// Gather information about aliases we need to print
//////////////////////////////
// Emit the method that prints the alias instruction.
std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
@ -809,7 +826,22 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) {
case CodeGenInstAlias::ResultOperand::K_Record: {
const Record *Rec = RO.getRecord();
StringRef ROName = RO.getName();
int PrintMethodIdx = -1;
// These two may have a PrintMethod, which we want to record (if it's
// the first time we've seen it) and provide an index for the aliasing
// code to use.
if (Rec->isSubClassOf("RegisterOperand") ||
Rec->isSubClassOf("Operand")) {
std::string PrintMethod = Rec->getValueAsString("PrintMethod");
if (PrintMethod != "" && PrintMethod != "printOperand") {
PrintMethodIdx = std::find(PrintMethods.begin(),
PrintMethods.end(), PrintMethod) -
PrintMethods.begin();
if (static_cast<unsigned>(PrintMethodIdx) == PrintMethods.size())
PrintMethods.push_back(PrintMethod);
}
}
if (Rec->isSubClassOf("RegisterOperand"))
Rec = Rec->getValueAsDef("RegClass");
@ -818,7 +850,7 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) {
IAP->addCond(Cond);
if (!IAP->isOpMapped(ROName)) {
IAP->addOperand(ROName, i);
IAP->addOperand(ROName, i, PrintMethodIdx);
Record *R = CGA->ResultOperands[i].getRecord();
if (R->isSubClassOf("RegisterOperand"))
R = R->getValueAsDef("RegClass");
@ -833,12 +865,9 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) {
IAP->addCond(Cond);
}
} else {
assert(Rec->isSubClassOf("Operand") && "Unexpected operand!");
// FIXME: We may need to handle these situations.
delete IAP;
IAP = nullptr;
CantHandle = true;
break;
// Assume all printable operands are desired for now. This can be
// overridden in the InstAlias instantiation if neccessary.
IAP->addOperand(ROName, i, PrintMethodIdx);
}
break;
@ -878,6 +907,10 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) {
}
}
//////////////////////////////
// Write out the printAliasInstr function
//////////////////////////////
std::string Header;
raw_string_ostream HeaderO(Header);
@ -951,7 +984,13 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) {
O << " do {\n";
O << " if (AsmString[I] == '$') {\n";
O << " ++I;\n";
O << " printOperand(MI, unsigned(AsmString[I++]) - 1, OS);\n";
O << " if (AsmString[I] == (char)0xff) {\n";
O << " ++I;\n";
O << " int OpIdx = AsmString[I++] - 1;\n";
O << " int PrintMethodIdx = AsmString[I++] - 1;\n";
O << " printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS);\n";
O << " } else\n";
O << " printOperand(MI, unsigned(AsmString[I++]) - 1, OS);\n";
O << " } else {\n";
O << " OS << AsmString[I++];\n";
O << " }\n";
@ -961,6 +1000,28 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) {
O << " return true;\n";
O << "}\n\n";
//////////////////////////////
// Write out the printCustomAliasOperand function
//////////////////////////////
O << "void " << Target.getName() << ClassName << "::"
<< "printCustomAliasOperand(\n"
<< " const MCInst *MI, unsigned OpIdx,\n"
<< " unsigned PrintMethodIdx, raw_ostream &OS) {\n"
<< " switch (PrintMethodIdx) {\n"
<< " default:\n"
<< " llvm_unreachable(\"Unknown PrintMethod kind\");\n"
<< " break;\n";
for (unsigned i = 0; i < PrintMethods.size(); ++i) {
O << " case " << i << ":\n"
<< " " << PrintMethods[i] << "(MI, OpIdx, OS);\n"
<< " break;\n";
}
O << " }\n"
<< "}\n\n";
O << "#endif // PRINT_ALIAS_INSTR\n";
}