mirror of
https://github.com/RPCS3/llvm.git
synced 2024-12-17 17:06:59 +00:00
Make getPhysicalRegisterRegClass non-virtual. Should be able to remove it soon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108094 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
db77609991
commit
d6d7abaf4e
@ -321,7 +321,7 @@ public:
|
||||
/// getPhysicalRegisterRegClass - Returns the Register Class of a physical
|
||||
/// register of the given type. If type is EVT::Other, then just return any
|
||||
/// register class the register belongs to.
|
||||
virtual const TargetRegisterClass *
|
||||
const TargetRegisterClass *
|
||||
getPhysicalRegisterRegClass(unsigned Reg, EVT VT = MVT::Other) const;
|
||||
|
||||
/// getMinimalPhysRegClass - Returns the Register Class of a physical
|
||||
|
@ -68,21 +68,6 @@ void Thumb1RegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB,
|
||||
.addConstantPoolIndex(Idx).addImm(Pred).addReg(PredReg);
|
||||
}
|
||||
|
||||
const TargetRegisterClass*
|
||||
Thumb1RegisterInfo::getPhysicalRegisterRegClass(unsigned Reg, EVT VT) const {
|
||||
if (isARMLowRegister(Reg))
|
||||
return ARM::tGPRRegisterClass;
|
||||
switch (Reg) {
|
||||
default:
|
||||
break;
|
||||
case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11:
|
||||
case ARM::R12: case ARM::SP: case ARM::LR: case ARM::PC:
|
||||
return ARM::GPRRegisterClass;
|
||||
}
|
||||
|
||||
return TargetRegisterInfo::getPhysicalRegisterRegClass(Reg, VT);
|
||||
}
|
||||
|
||||
bool Thumb1RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
|
||||
const MachineFrameInfo *FFI = MF.getFrameInfo();
|
||||
unsigned CFSize = FFI->getMaxCallFrameSize();
|
||||
|
@ -38,9 +38,6 @@ public:
|
||||
unsigned PredReg = 0) const;
|
||||
|
||||
/// Code Generation virtual methods...
|
||||
const TargetRegisterClass *
|
||||
getPhysicalRegisterRegClass(unsigned Reg, EVT VT = MVT::Other) const;
|
||||
|
||||
bool hasReservedCallFrame(MachineFunction &MF) const;
|
||||
|
||||
void eliminateCallFramePseudoInstr(MachineFunction &MF,
|
||||
|
@ -75,25 +75,6 @@ BlackfinRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
|
||||
return Reserved;
|
||||
}
|
||||
|
||||
const TargetRegisterClass*
|
||||
BlackfinRegisterInfo::getPhysicalRegisterRegClass(unsigned reg, EVT VT) const {
|
||||
assert(isPhysicalRegister(reg) && "reg must be a physical register");
|
||||
|
||||
// Pick the smallest register class of the right type that contains
|
||||
// this physreg.
|
||||
const TargetRegisterClass* BestRC = 0;
|
||||
for (regclass_iterator I = regclass_begin(), E = regclass_end();
|
||||
I != E; ++I) {
|
||||
const TargetRegisterClass* RC = *I;
|
||||
if ((VT == MVT::Other || RC->hasType(VT)) && RC->contains(reg) &&
|
||||
(!BestRC || RC->getNumRegs() < BestRC->getNumRegs()))
|
||||
BestRC = RC;
|
||||
}
|
||||
|
||||
assert(BestRC && "Couldn't find the register class");
|
||||
return BestRC;
|
||||
}
|
||||
|
||||
// hasFP - Return true if the specified function should have a dedicated frame
|
||||
// pointer register. This is true if the function has variable sized allocas or
|
||||
// if frame pointer elimination is disabled.
|
||||
|
@ -41,9 +41,6 @@ namespace llvm {
|
||||
return &BF::PRegClass;
|
||||
}
|
||||
|
||||
const TargetRegisterClass *getPhysicalRegisterRegClass(unsigned reg,
|
||||
EVT VT) const;
|
||||
|
||||
bool hasFP(const MachineFunction &MF) const;
|
||||
|
||||
// bool hasReservedCallFrame(MachineFunction &MF) const;
|
||||
|
Loading…
Reference in New Issue
Block a user