From d7599ee3b114e09f141e158387cbd5848af7951a Mon Sep 17 00:00:00 2001 From: Jonas Paulsson Date: Mon, 23 Jan 2017 14:09:58 +0000 Subject: [PATCH] [SystemZ] Mark vector immediate load instructions with useful flags. Vector immediate load instructions should have the isAsCheapAsAMove, isMoveImm and isReMaterializable flags set. With them, these instruction will get hoisted out of loops. Review: Ulrich Weigand git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292790 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/SystemZ/SystemZInstrVector.td | 38 +++++++++++++----------- lib/Target/SystemZ/SystemZScheduleZ13.td | 2 +- 2 files changed, 22 insertions(+), 18 deletions(-) diff --git a/lib/Target/SystemZ/SystemZInstrVector.td b/lib/Target/SystemZ/SystemZInstrVector.td index 738ea7a3372..0158fe6aec0 100644 --- a/lib/Target/SystemZ/SystemZInstrVector.td +++ b/lib/Target/SystemZ/SystemZInstrVector.td @@ -56,17 +56,28 @@ def : VectorExtractSubreg; //===----------------------------------------------------------------------===// let Predicates = [FeatureVector] in { - // Generate byte mask. - def VZERO : InherentVRIa<"vzero", 0xE744, 0>; - def VONE : InherentVRIa<"vone", 0xE744, 0xffff>; - def VGBM : UnaryVRIa<"vgbm", 0xE744, z_byte_mask, v128b, imm32zx16>; + let hasSideEffects = 0, isAsCheapAsAMove = 1, isMoveImm = 1, + isReMaterializable = 1 in { - // Generate mask. - def VGM : BinaryVRIbGeneric<"vgm", 0xE746>; - def VGMB : BinaryVRIb<"vgmb", 0xE746, z_rotate_mask, v128b, 0>; - def VGMH : BinaryVRIb<"vgmh", 0xE746, z_rotate_mask, v128h, 1>; - def VGMF : BinaryVRIb<"vgmf", 0xE746, z_rotate_mask, v128f, 2>; - def VGMG : BinaryVRIb<"vgmg", 0xE746, z_rotate_mask, v128g, 3>; + // Generate byte mask. + def VZERO : InherentVRIa<"vzero", 0xE744, 0>; + def VONE : InherentVRIa<"vone", 0xE744, 0xffff>; + def VGBM : UnaryVRIa<"vgbm", 0xE744, z_byte_mask, v128b, imm32zx16>; + + // Generate mask. + def VGM : BinaryVRIbGeneric<"vgm", 0xE746>; + def VGMB : BinaryVRIb<"vgmb", 0xE746, z_rotate_mask, v128b, 0>; + def VGMH : BinaryVRIb<"vgmh", 0xE746, z_rotate_mask, v128h, 1>; + def VGMF : BinaryVRIb<"vgmf", 0xE746, z_rotate_mask, v128f, 2>; + def VGMG : BinaryVRIb<"vgmg", 0xE746, z_rotate_mask, v128g, 3>; + + // Replicate immediate. + def VREPI : UnaryVRIaGeneric<"vrepi", 0xE745, imm32sx16>; + def VREPIB : UnaryVRIa<"vrepib", 0xE745, z_replicate, v128b, imm32sx16, 0>; + def VREPIH : UnaryVRIa<"vrepih", 0xE745, z_replicate, v128h, imm32sx16, 1>; + def VREPIF : UnaryVRIa<"vrepif", 0xE745, z_replicate, v128f, imm32sx16, 2>; + def VREPIG : UnaryVRIa<"vrepig", 0xE745, z_replicate, v128g, imm32sx16, 3>; + } // Load element immediate. // @@ -86,13 +97,6 @@ let Predicates = [FeatureVector] in { def VLEIG : TernaryVRIa<"vleig", 0xE742, z_vector_insert, v128g, v128g, imm64sx16, imm32zx1>; } - - // Replicate immediate. - def VREPI : UnaryVRIaGeneric<"vrepi", 0xE745, imm32sx16>; - def VREPIB : UnaryVRIa<"vrepib", 0xE745, z_replicate, v128b, imm32sx16, 0>; - def VREPIH : UnaryVRIa<"vrepih", 0xE745, z_replicate, v128h, imm32sx16, 1>; - def VREPIF : UnaryVRIa<"vrepif", 0xE745, z_replicate, v128f, imm32sx16, 2>; - def VREPIG : UnaryVRIa<"vrepig", 0xE745, z_replicate, v128g, imm32sx16, 3>; } //===----------------------------------------------------------------------===// diff --git a/lib/Target/SystemZ/SystemZScheduleZ13.td b/lib/Target/SystemZ/SystemZScheduleZ13.td index e97d61d8355..7aee6f52e9a 100644 --- a/lib/Target/SystemZ/SystemZScheduleZ13.td +++ b/lib/Target/SystemZ/SystemZScheduleZ13.td @@ -855,8 +855,8 @@ def : InstRW<[VecXsPm], (instregex "VZERO$")>; def : InstRW<[VecXsPm], (instregex "VONE$")>; def : InstRW<[VecXsPm], (instregex "VGBM$")>; def : InstRW<[VecXsPm], (instregex "VGM(B|F|G|H)?$")>; -def : InstRW<[VecXsPm], (instregex "VLEI(B|F|G|H)$")>; def : InstRW<[VecXsPm], (instregex "VREPI(B|F|G|H)?$")>; +def : InstRW<[VecXsPm], (instregex "VLEI(B|F|G|H)$")>; //===----------------------------------------------------------------------===// // Vector: Loads