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AArch64: Simplify emitEpilogue() and related code; NFC

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This is in preparation to an upcoming patch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255872 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matthias Braun 2015-12-17 03:18:47 +00:00
parent 4151f0d8f9
commit d7696fd2cb
1 changed files with 25 additions and 24 deletions
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49
lib/Target/AArch64/AArch64FrameLowering.cpp
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@ -515,23 +515,24 @@ static bool isCalleeSavedRegister(unsigned Reg, const MCPhysReg *CSRegs) {
return false;
}
static bool isCSRestore(MachineInstr *MI, const MCPhysReg *CSRegs) {
/// Checks whether the given instruction restores callee save registers
/// and if so returns how many.
static unsigned getNumCSRestores(MachineInstr &MI, const MCPhysReg *CSRegs) {
unsigned RtIdx = 0;
if (MI->getOpcode() == AArch64::LDPXpost ||
MI->getOpcode() == AArch64::LDPDpost)
switch (MI.getOpcode()) {
case AArch64::LDPXpost:
case AArch64::LDPDpost:
RtIdx = 1;
if (MI->getOpcode() == AArch64::LDPXpost ||
MI->getOpcode() == AArch64::LDPDpost ||
MI->getOpcode() == AArch64::LDPXi || MI->getOpcode() == AArch64::LDPDi) {
if (!isCalleeSavedRegister(MI->getOperand(RtIdx).getReg(), CSRegs) ||
!isCalleeSavedRegister(MI->getOperand(RtIdx + 1).getReg(), CSRegs) ||
MI->getOperand(RtIdx + 2).getReg() != AArch64::SP)
return false;
return true;
// FALLTHROUGH
case AArch64::LDPXi:
case AArch64::LDPDi:
if (!isCalleeSavedRegister(MI.getOperand(RtIdx).getReg(), CSRegs) ||
!isCalleeSavedRegister(MI.getOperand(RtIdx + 1).getReg(), CSRegs) ||
MI.getOperand(RtIdx + 2).getReg() != AArch64::SP)
return 0;
return 2;
}
return false;
return 0;
}
void AArch64FrameLowering::emitEpilogue(MachineFunction &MF,
@ -586,7 +587,7 @@ void AArch64FrameLowering::emitEpilogue(MachineFunction &MF,
// ---------------------| --- |
// | | | |
// | CalleeSavedReg | | |
// | (NumRestores * 16) | | |
// | (NumRestores * 8) | | |
// | | | |
// ---------------------| | NumBytes
// | | StackSize (StackAdjustUp)
@ -607,17 +608,17 @@ void AArch64FrameLowering::emitEpilogue(MachineFunction &MF,
// Move past the restores of the callee-saved registers.
MachineBasicBlock::iterator LastPopI = MBB.getFirstTerminator();
const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF);
if (LastPopI != MBB.begin()) {
do {
++NumRestores;
--LastPopI;
} while (LastPopI != MBB.begin() && isCSRestore(LastPopI, CSRegs));
if (!isCSRestore(LastPopI, CSRegs)) {
MachineBasicBlock::iterator Begin = MBB.begin();
while (LastPopI != Begin) {
--LastPopI;
unsigned Restores = getNumCSRestores(*LastPopI, CSRegs);
NumRestores += Restores;
if (Restores == 0) {
++LastPopI;
--NumRestores;
break;
}
}
NumBytes -= NumRestores * 16;
NumBytes -= NumRestores * 8;
assert(NumBytes >= 0 && "Negative stack allocation size!?");
if (!hasFP(MF)) {
@ -635,7 +636,7 @@ void AArch64FrameLowering::emitEpilogue(MachineFunction &MF,
// be able to save any instructions.
if (NumBytes || MFI->hasVarSizedObjects())
emitFrameOffset(MBB, LastPopI, DL, AArch64::SP, AArch64::FP,
-(NumRestores - 1) * 16, TII, MachineInstr::NoFlags);
-(NumRestores - 2) * 8, TII, MachineInstr::NoFlags);
}
/// getFrameIndexReference - Provide a base+offset reference to an FI slot for