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[X86][SSE] Add PR30780 test cases

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Broadcast of sign/zero extended scalars resulting in unnecessary vector constants

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321584 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Simon Pilgrim 2017-12-30 11:51:45 +00:00
parent 060d035c28
commit d771b00e32
2 changed files with 177 additions and 0 deletions
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103
test/CodeGen/X86/build-vector-128.ll
View File

@ -409,3 +409,106 @@ define <16 x i8> @test_buildvector_v16i8(i8 %a0, i8 %a1, i8 %a2, i8 %a3, i8 %a4,
%ins15 = insertelement <16 x i8> %ins14, i8 %a15, i32 15 %ins15 = insertelement <16 x i8> %ins14, i8 %a15, i32 15
ret <16 x i8> %ins15 ret <16 x i8> %ins15
} }
; PR30780
define <4 x i32> @test_buildvector_v4i32_splat_sext_i8(i8 %in) {
; SSE-32-LABEL: test_buildvector_v4i32_splat_sext_i8:
; SSE-32: # %bb.0:
; SSE-32-NEXT: movsbl {{[0-9]+}}(%esp), %eax
; SSE-32-NEXT: movd %eax, %xmm0
; SSE-32-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
; SSE-32-NEXT: retl
;
; SSE-64-LABEL: test_buildvector_v4i32_splat_sext_i8:
; SSE-64: # %bb.0:
; SSE-64-NEXT: movsbl %dil, %eax
; SSE-64-NEXT: movd %eax, %xmm0
; SSE-64-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
; SSE-64-NEXT: retq
;
; AVX1-32-LABEL: test_buildvector_v4i32_splat_sext_i8:
; AVX1-32: # %bb.0:
; AVX1-32-NEXT: movsbl {{[0-9]+}}(%esp), %eax
; AVX1-32-NEXT: vmovd %eax, %xmm0
; AVX1-32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
; AVX1-32-NEXT: retl
;
; AVX1-64-LABEL: test_buildvector_v4i32_splat_sext_i8:
; AVX1-64: # %bb.0:
; AVX1-64-NEXT: movsbl %dil, %eax
; AVX1-64-NEXT: vmovd %eax, %xmm0
; AVX1-64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
; AVX1-64-NEXT: retq
;
; AVX2-32-LABEL: test_buildvector_v4i32_splat_sext_i8:
; AVX2-32: # %bb.0:
; AVX2-32-NEXT: movsbl {{[0-9]+}}(%esp), %eax
; AVX2-32-NEXT: vmovd %eax, %xmm0
; AVX2-32-NEXT: vpbroadcastd %xmm0, %xmm0
; AVX2-32-NEXT: retl
;
; AVX2-64-LABEL: test_buildvector_v4i32_splat_sext_i8:
; AVX2-64: # %bb.0:
; AVX2-64-NEXT: movsbl %dil, %eax
; AVX2-64-NEXT: vmovd %eax, %xmm0
; AVX2-64-NEXT: vpbroadcastd %xmm0, %xmm0
; AVX2-64-NEXT: retq
%ext = sext i8 %in to i32
%insert = insertelement <4 x i32> undef, i32 %ext, i32 0
%splat = shufflevector <4 x i32> %insert, <4 x i32> undef, <4 x i32> zeroinitializer
ret <4 x i32> %splat
}
define <4 x i32> @test_buildvector_v4i32_splat_zext_i8(i8 %in) {
; SSE-32-LABEL: test_buildvector_v4i32_splat_zext_i8:
; SSE-32: # %bb.0:
; SSE-32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; SSE-32-NEXT: movd %eax, %xmm0
; SSE-32-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
; SSE-32-NEXT: retl
;
; SSE2-64-LABEL: test_buildvector_v4i32_splat_zext_i8:
; SSE2-64: # %bb.0:
; SSE2-64-NEXT: movd %edi, %xmm0
; SSE2-64-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
; SSE2-64-NEXT: pand {{.*}}(%rip), %xmm0
; SSE2-64-NEXT: retq
;
; SSE41-64-LABEL: test_buildvector_v4i32_splat_zext_i8:
; SSE41-64: # %bb.0:
; SSE41-64-NEXT: movd %edi, %xmm0
; SSE41-64-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[0],zero,zero,zero,xmm0[0],zero,zero,zero,xmm0[0],zero,zero,zero
; SSE41-64-NEXT: retq
;
; AVX1-32-LABEL: test_buildvector_v4i32_splat_zext_i8:
; AVX1-32: # %bb.0:
; AVX1-32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; AVX1-32-NEXT: vmovd %eax, %xmm0
; AVX1-32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
; AVX1-32-NEXT: retl
;
; AVX1-64-LABEL: test_buildvector_v4i32_splat_zext_i8:
; AVX1-64: # %bb.0:
; AVX1-64-NEXT: vmovd %edi, %xmm0
; AVX1-64-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[0],zero,zero,zero,xmm0[0],zero,zero,zero,xmm0[0],zero,zero,zero
; AVX1-64-NEXT: retq
;
; AVX2-32-LABEL: test_buildvector_v4i32_splat_zext_i8:
; AVX2-32: # %bb.0:
; AVX2-32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; AVX2-32-NEXT: vmovd %eax, %xmm0
; AVX2-32-NEXT: vpbroadcastd %xmm0, %xmm0
; AVX2-32-NEXT: retl
;
; AVX2-64-LABEL: test_buildvector_v4i32_splat_zext_i8:
; AVX2-64: # %bb.0:
; AVX2-64-NEXT: movzbl %dil, %eax
; AVX2-64-NEXT: vmovd %eax, %xmm0
; AVX2-64-NEXT: vpbroadcastd %xmm0, %xmm0
; AVX2-64-NEXT: retq
%ext = zext i8 %in to i32
%insert = insertelement <4 x i32> undef, i32 %ext, i32 0
%splat = shufflevector <4 x i32> %insert, <4 x i32> undef, <4 x i32> zeroinitializer
ret <4 x i32> %splat
}

74
test/CodeGen/X86/build-vector-256.ll
View File

@ -411,3 +411,77 @@ define <32 x i8> @test_buildvector_v32i8(i8 %a0, i8 %a1, i8 %a2, i8 %a3, i8 %a4,
%ins31 = insertelement <32 x i8> %ins30, i8 %a31, i32 31 %ins31 = insertelement <32 x i8> %ins30, i8 %a31, i32 31
ret <32 x i8> %ins31 ret <32 x i8> %ins31
} }
; PR30780
define <8 x i32> @test_buildvector_v8i32_splat_sext_i8(i8 %in) {
; AVX1-32-LABEL: test_buildvector_v8i32_splat_sext_i8:
; AVX1-32: # %bb.0:
; AVX1-32-NEXT: movsbl {{[0-9]+}}(%esp), %eax
; AVX1-32-NEXT: vmovd %eax, %xmm0
; AVX1-32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
; AVX1-32-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
; AVX1-32-NEXT: retl
;
; AVX1-64-LABEL: test_buildvector_v8i32_splat_sext_i8:
; AVX1-64: # %bb.0:
; AVX1-64-NEXT: movsbl %dil, %eax
; AVX1-64-NEXT: vmovd %eax, %xmm0
; AVX1-64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
; AVX1-64-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
; AVX1-64-NEXT: retq
;
; AVX2-32-LABEL: test_buildvector_v8i32_splat_sext_i8:
; AVX2-32: # %bb.0:
; AVX2-32-NEXT: movsbl {{[0-9]+}}(%esp), %eax
; AVX2-32-NEXT: vmovd %eax, %xmm0
; AVX2-32-NEXT: vpbroadcastd %xmm0, %ymm0
; AVX2-32-NEXT: retl
;
; AVX2-64-LABEL: test_buildvector_v8i32_splat_sext_i8:
; AVX2-64: # %bb.0:
; AVX2-64-NEXT: movsbl %dil, %eax
; AVX2-64-NEXT: vmovd %eax, %xmm0
; AVX2-64-NEXT: vpbroadcastd %xmm0, %ymm0
; AVX2-64-NEXT: retq
%ext = sext i8 %in to i32
%insert = insertelement <8 x i32> undef, i32 %ext, i32 0
%splat = shufflevector <8 x i32> %insert, <8 x i32> undef, <8 x i32> zeroinitializer
ret <8 x i32> %splat
}
define <8 x i32> @test_buildvector_v8i32_splat_zext_i8(i8 %in) {
; AVX1-32-LABEL: test_buildvector_v8i32_splat_zext_i8:
; AVX1-32: # %bb.0:
; AVX1-32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; AVX1-32-NEXT: vmovd %eax, %xmm0
; AVX1-32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
; AVX1-32-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
; AVX1-32-NEXT: retl
;
; AVX1-64-LABEL: test_buildvector_v8i32_splat_zext_i8:
; AVX1-64: # %bb.0:
; AVX1-64-NEXT: vmovd %edi, %xmm0
; AVX1-64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
; AVX1-64-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
; AVX1-64-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
; AVX1-64-NEXT: retq
;
; AVX2-32-LABEL: test_buildvector_v8i32_splat_zext_i8:
; AVX2-32: # %bb.0:
; AVX2-32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; AVX2-32-NEXT: vmovd %eax, %xmm0
; AVX2-32-NEXT: vpbroadcastd %xmm0, %ymm0
; AVX2-32-NEXT: retl
;
; AVX2-64-LABEL: test_buildvector_v8i32_splat_zext_i8:
; AVX2-64: # %bb.0:
; AVX2-64-NEXT: movzbl %dil, %eax
; AVX2-64-NEXT: vmovd %eax, %xmm0
; AVX2-64-NEXT: vpbroadcastd %xmm0, %ymm0
; AVX2-64-NEXT: retq
%ext = zext i8 %in to i32
%insert = insertelement <8 x i32> undef, i32 %ext, i32 0
%splat = shufflevector <8 x i32> %insert, <8 x i32> undef, <8 x i32> zeroinitializer
ret <8 x i32> %splat
}