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Remove a check from ARM shifted operand isel helper methods, which were blocking

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merging an lsl #2 that has multiple uses on A9. This shift is free, so there is
no problem merging it in multiple places. Other unprofitable shifts will not be
merged.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141247 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Cameron Zwarich 2011-10-05 23:38:50 +00:00
parent 5cbef19a1d
commit d78ebe1e12
2 changed files with 4 additions and 15 deletions
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10
lib/Target/ARM/ARMISelDAGToDAG.cpp
View File

@ -519,11 +519,6 @@ bool ARMDAGToDAGISel::SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset,
return false;
}
if (Subtarget->isCortexA9() && !N.hasOneUse()) {
// Compute R +/- (R << N) and reuse it.
return false;
}
// Otherwise this is R +/- [possibly shifted] R.
ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::SUB ? ARM_AM::sub:ARM_AM::add;
ARM_AM::ShiftOpc ShOpcVal =
@ -1286,11 +1281,6 @@ bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDValue N,
return false;
}
if (Subtarget->isCortexA9() && !N.hasOneUse()) {
// Compute R + (R << [1,2,3]) and reuse it.
return false;
}
// Look for (R + R) or (R + (R << [1,2,3])).
unsigned ShAmt = 0;
Base = N.getOperand(0);

9
test/CodeGen/ARM/shifter_operand.ll
View File

@ -54,13 +54,12 @@ declare i8* @malloc(...)
define fastcc void @test4(i16 %addr) nounwind {
entry:
; A8: test4:
; A8: ldr r2, [r0, r1, lsl #2]
; A8: str r2, [r0, r1, lsl #2]
; A8: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]
; A8: str [[REG]], [r0, r1, lsl #2]
; A9: test4:
; A9: add r0, r0, r{{[0-9]+}}, lsl #2
; A9: ldr r1, [r0]
; A9: str r1, [r0]
; A9: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]
; A9: str [[REG]], [r0, r1, lsl #2]
%0 = tail call i8* (...)* @malloc(i32 undef) nounwind
%1 = bitcast i8* %0 to i32*
%2 = sext i16 %addr to i32