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[Hexagon] Add utility functions to detect sign- and zero-extending loads
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@260698 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Krzysztof Parzyszek
parent
c006b1e101
commit
d832030ace
@ -2227,6 +2227,85 @@ bool HexagonInstrInfo::isSaveCalleeSavedRegsCall(const MachineInstr *MI) const {
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}
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bool HexagonInstrInfo::isSignExtendingLoad(const MachineInstr* MI) const {
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switch (MI->getOpcode()) {
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// Byte
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case Hexagon::L2_loadrb_io:
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case Hexagon::L4_loadrb_ur:
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case Hexagon::L4_loadrb_ap:
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case Hexagon::L2_loadrb_pr:
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case Hexagon::L2_loadrb_pbr:
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case Hexagon::L2_loadrb_pi:
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case Hexagon::L2_loadrb_pci:
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case Hexagon::L2_loadrb_pcr:
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case Hexagon::L2_loadbsw2_io:
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case Hexagon::L4_loadbsw2_ur:
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case Hexagon::L4_loadbsw2_ap:
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case Hexagon::L2_loadbsw2_pr:
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case Hexagon::L2_loadbsw2_pbr:
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case Hexagon::L2_loadbsw2_pi:
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case Hexagon::L2_loadbsw2_pci:
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case Hexagon::L2_loadbsw2_pcr:
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case Hexagon::L2_loadbsw4_io:
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case Hexagon::L4_loadbsw4_ur:
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case Hexagon::L4_loadbsw4_ap:
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case Hexagon::L2_loadbsw4_pr:
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case Hexagon::L2_loadbsw4_pbr:
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case Hexagon::L2_loadbsw4_pi:
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case Hexagon::L2_loadbsw4_pci:
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case Hexagon::L2_loadbsw4_pcr:
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case Hexagon::L4_loadrb_rr:
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case Hexagon::L2_ploadrbt_io:
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case Hexagon::L2_ploadrbt_pi:
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case Hexagon::L2_ploadrbf_io:
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case Hexagon::L2_ploadrbf_pi:
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case Hexagon::L2_ploadrbtnew_io:
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case Hexagon::L2_ploadrbfnew_io:
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case Hexagon::L4_ploadrbt_rr:
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case Hexagon::L4_ploadrbf_rr:
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case Hexagon::L4_ploadrbtnew_rr:
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case Hexagon::L4_ploadrbfnew_rr:
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case Hexagon::L2_ploadrbtnew_pi:
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case Hexagon::L2_ploadrbfnew_pi:
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case Hexagon::L4_ploadrbt_abs:
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case Hexagon::L4_ploadrbf_abs:
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case Hexagon::L4_ploadrbtnew_abs:
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case Hexagon::L4_ploadrbfnew_abs:
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case Hexagon::L2_loadrbgp:
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// Half
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case Hexagon::L2_loadrh_io:
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case Hexagon::L4_loadrh_ur:
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case Hexagon::L4_loadrh_ap:
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case Hexagon::L2_loadrh_pr:
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case Hexagon::L2_loadrh_pbr:
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case Hexagon::L2_loadrh_pi:
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case Hexagon::L2_loadrh_pci:
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case Hexagon::L2_loadrh_pcr:
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case Hexagon::L4_loadrh_rr:
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case Hexagon::L2_ploadrht_io:
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case Hexagon::L2_ploadrht_pi:
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case Hexagon::L2_ploadrhf_io:
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case Hexagon::L2_ploadrhf_pi:
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case Hexagon::L2_ploadrhtnew_io:
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case Hexagon::L2_ploadrhfnew_io:
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case Hexagon::L4_ploadrht_rr:
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case Hexagon::L4_ploadrhf_rr:
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case Hexagon::L4_ploadrhtnew_rr:
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case Hexagon::L4_ploadrhfnew_rr:
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case Hexagon::L2_ploadrhtnew_pi:
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case Hexagon::L2_ploadrhfnew_pi:
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case Hexagon::L4_ploadrht_abs:
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case Hexagon::L4_ploadrhf_abs:
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case Hexagon::L4_ploadrhtnew_abs:
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case Hexagon::L4_ploadrhfnew_abs:
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case Hexagon::L2_loadrhgp:
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return true;
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default:
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return false;
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}
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}
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bool HexagonInstrInfo::isSolo(const MachineInstr* MI) const {
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const uint64_t F = MI->getDesc().TSFlags;
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return (F >> HexagonII::SoloPos) & HexagonII::SoloMask;
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@ -2464,7 +2543,7 @@ bool HexagonInstrInfo::isValidOffset(unsigned Opcode, int Offset,
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case Hexagon::L4_or_memopb_io :
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return (0 <= Offset && Offset <= 63);
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// LDri_pred and STriw_pred are pseudo operations, so it has to take offset of
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// LDriw_xxx and STriw_xxx are pseudo operations, so it has to take offset of
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// any size. Later pass knows how to handle it.
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case Hexagon::STriw_pred:
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case Hexagon::LDriw_pred:
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@ -2551,6 +2630,85 @@ bool HexagonInstrInfo::isVecUsableNextPacket(const MachineInstr *ProdMI,
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}
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bool HexagonInstrInfo::isZeroExtendingLoad(const MachineInstr* MI) const {
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switch (MI->getOpcode()) {
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// Byte
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case Hexagon::L2_loadrub_io:
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case Hexagon::L4_loadrub_ur:
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case Hexagon::L4_loadrub_ap:
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case Hexagon::L2_loadrub_pr:
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case Hexagon::L2_loadrub_pbr:
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case Hexagon::L2_loadrub_pi:
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case Hexagon::L2_loadrub_pci:
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case Hexagon::L2_loadrub_pcr:
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case Hexagon::L2_loadbzw2_io:
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case Hexagon::L4_loadbzw2_ur:
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case Hexagon::L4_loadbzw2_ap:
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case Hexagon::L2_loadbzw2_pr:
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case Hexagon::L2_loadbzw2_pbr:
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case Hexagon::L2_loadbzw2_pi:
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case Hexagon::L2_loadbzw2_pci:
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case Hexagon::L2_loadbzw2_pcr:
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case Hexagon::L2_loadbzw4_io:
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case Hexagon::L4_loadbzw4_ur:
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case Hexagon::L4_loadbzw4_ap:
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case Hexagon::L2_loadbzw4_pr:
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case Hexagon::L2_loadbzw4_pbr:
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case Hexagon::L2_loadbzw4_pi:
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case Hexagon::L2_loadbzw4_pci:
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case Hexagon::L2_loadbzw4_pcr:
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case Hexagon::L4_loadrub_rr:
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case Hexagon::L2_ploadrubt_io:
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case Hexagon::L2_ploadrubt_pi:
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case Hexagon::L2_ploadrubf_io:
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case Hexagon::L2_ploadrubf_pi:
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case Hexagon::L2_ploadrubtnew_io:
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case Hexagon::L2_ploadrubfnew_io:
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case Hexagon::L4_ploadrubt_rr:
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case Hexagon::L4_ploadrubf_rr:
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case Hexagon::L4_ploadrubtnew_rr:
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case Hexagon::L4_ploadrubfnew_rr:
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case Hexagon::L2_ploadrubtnew_pi:
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case Hexagon::L2_ploadrubfnew_pi:
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case Hexagon::L4_ploadrubt_abs:
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case Hexagon::L4_ploadrubf_abs:
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case Hexagon::L4_ploadrubtnew_abs:
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case Hexagon::L4_ploadrubfnew_abs:
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case Hexagon::L2_loadrubgp:
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// Half
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case Hexagon::L2_loadruh_io:
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case Hexagon::L4_loadruh_ur:
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case Hexagon::L4_loadruh_ap:
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case Hexagon::L2_loadruh_pr:
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case Hexagon::L2_loadruh_pbr:
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case Hexagon::L2_loadruh_pi:
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case Hexagon::L2_loadruh_pci:
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case Hexagon::L2_loadruh_pcr:
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case Hexagon::L4_loadruh_rr:
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case Hexagon::L2_ploadruht_io:
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case Hexagon::L2_ploadruht_pi:
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case Hexagon::L2_ploadruhf_io:
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case Hexagon::L2_ploadruhf_pi:
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case Hexagon::L2_ploadruhtnew_io:
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case Hexagon::L2_ploadruhfnew_io:
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case Hexagon::L4_ploadruht_rr:
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case Hexagon::L4_ploadruhf_rr:
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case Hexagon::L4_ploadruhtnew_rr:
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case Hexagon::L4_ploadruhfnew_rr:
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case Hexagon::L2_ploadruhtnew_pi:
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case Hexagon::L2_ploadruhfnew_pi:
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case Hexagon::L4_ploadruht_abs:
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case Hexagon::L4_ploadruhf_abs:
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case Hexagon::L4_ploadruhtnew_abs:
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case Hexagon::L4_ploadruhfnew_abs:
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case Hexagon::L2_loadruhgp:
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return true;
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default:
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return false;
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}
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}
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/// \brief Can these instructions execute at the same time in a bundle.
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bool HexagonInstrInfo::canExecuteInBundle(const MachineInstr *First,
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const MachineInstr *Second) const {
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@ -309,6 +309,7 @@ public:
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bool isPredicateLate(unsigned Opcode) const;
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bool isPredictedTaken(unsigned Opcode) const;
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bool isSaveCalleeSavedRegsCall(const MachineInstr *MI) const;
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bool isSignExtendingLoad(const MachineInstr *MI) const;
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bool isSolo(const MachineInstr* MI) const;
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bool isSpillPredRegOp(const MachineInstr *MI) const;
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bool isTC1(const MachineInstr *MI) const;
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@ -322,6 +323,7 @@ public:
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bool isVecALU(const MachineInstr *MI) const;
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bool isVecUsableNextPacket(const MachineInstr *ProdMI,
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const MachineInstr *ConsMI) const;
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bool isZeroExtendingLoad(const MachineInstr *MI) const;
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bool canExecuteInBundle(const MachineInstr *First,
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