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[mips] Correct the predicates of indexed floating point stores and loads.

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Also, fix the register class for microMIPS.

Reviewers: atanasyan, abeserminji, smaksimovic

Differential Revision: https://reviews.llvm.org/D46689


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332227 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Simon Dardis 2018-05-14 10:53:15 +00:00
parent 6cf914db39
commit d91853e2c4
5 changed files with 18 additions and 20 deletions
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23
lib/Target/Mips/MicroMipsInstrFPU.td
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@ -41,19 +41,18 @@ defm FMUL : ADDS_MMM<"mul.d", II_MUL_D, 1, fmul>,
defm FSUB : ADDS_MMM<"sub.d", II_SUB_D, 0, fsub>,
ADDS_FM_MM<1, 0x70>, ISA_MICROMIPS;
let DecoderNamespace = "MicroMips" in {
def LWXC1_MM : MMRel, LWXC1_FT<"lwxc1", FGR32Opnd, II_LWXC1, load>,
LWXC1_FM_MM<0x48>, ISA_MICROMIPS32_NOT_MIPS32R6;
def SWXC1_MM : MMRel, SWXC1_FT<"swxc1", FGR32Opnd, II_SWXC1, store>,
SWXC1_FM_MM<0x88>, ISA_MICROMIPS32_NOT_MIPS32R6;
def LUXC1_MM : MMRel, LWXC1_FT<"luxc1", FGR64Opnd, II_LUXC1>,
LWXC1_FM_MM<0x148>, FGR_64, ISA_MICROMIPS32_NOT_MIPS32R6;
def SUXC1_MM : MMRel, SWXC1_FT<"suxc1", FGR64Opnd, II_SUXC1>,
SWXC1_FM_MM<0x188>, FGR_64, ISA_MICROMIPS32_NOT_MIPS32R6;
}
let isCodeGenOnly = 1 in {
def LWXC1_MM : MMRel, LWXC1_FT<"lwxc1", FGR32Opnd, II_LWXC1, load>,
LWXC1_FM_MM<0x48>, ISA_MICROMIPS32_NOT_MIPS32R6;
def SWXC1_MM : MMRel, SWXC1_FT<"swxc1", FGR32Opnd, II_SWXC1, store>,
SWXC1_FM_MM<0x88>, ISA_MICROMIPS32_NOT_MIPS32R6;
// FIXME: These instruction definitions are incorrect. They should be 64-bit
// FPU only.
def LUXC1_MM : MMRel, LWXC1_FT<"luxc1", AFGR64Opnd, II_LUXC1>,
LWXC1_FM_MM<0x148>, ISA_MICROMIPS32_NOT_MIPS32R6;
def SUXC1_MM : MMRel, SWXC1_FT<"suxc1", AFGR64Opnd, II_SUXC1>,
SWXC1_FM_MM<0x188>, ISA_MICROMIPS32_NOT_MIPS32R6;
def FCMP_S32_MM : MMRel, CEQS_FT<"s", FGR32, II_C_CC_S, MipsFPCmp>,
CEQS_FM_MM<0>, ISA_MICROMIPS32_NOT_MIPS32R6 {
// FIXME: This is a required to work around the fact that these instructions

5
lib/Target/Mips/MipsInstrFPU.td
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@ -576,14 +576,15 @@ let DecoderNamespace="MipsFP64" in {
// Load/store doubleword indexed unaligned.
// FIXME: This instruction should not be defined for FGR_32.
let AdditionalPredicates = [IsNotNaCl] in {
let AdditionalPredicates = [IsNotNaCl, NotInMicroMips] in {
def LUXC1 : MMRel, LWXC1_FT<"luxc1", AFGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>,
INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_32;
def SUXC1 : MMRel, SWXC1_FT<"suxc1", AFGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>,
INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_32;
}
let DecoderNamespace="MipsFP64" in {
let AdditionalPredicates = [IsNotNaCl, NotInMicroMips],
DecoderNamespace="MipsFP64" in {
def LUXC164 : LWXC1_FT<"luxc1", FGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>,
INSN_MIPS5_32R2_NOT_32R6_64R6, FGR_64;
def SUXC164 : SWXC1_FT<"suxc1", FGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>,

2
test/MC/Disassembler/Mips/micromips32r3/valid-fp64-el.txt
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@ -19,3 +19,5 @@
0x02 0x54 0x7b 0x1b # CHECK: cvt.s.d $f0, $f2
0x82 0x54 0x3b 0x01 # CHECK: cvt.l.s $f4, $f2
0x82 0x54 0x3b 0x41 # CHECK: cvt.l.d $f4, $f2
0x85 0x54 0x48 0x21 # CHECK: luxc1 $f4, $4($5)
0x85 0x54 0x88 0x21 # CHECK: suxc1 $f4, $4($5)

2
test/MC/Disassembler/Mips/micromips32r3/valid-fp64.txt
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@ -19,3 +19,5 @@
0x54 0x02 0x1b 0x7b # CHECK: cvt.s.d $f0, $f2
0x54 0x82 0x01 0x3b # CHECK: cvt.l.s $f4, $f2
0x54 0x82 0x41 0x3b # CHECK: cvt.l.d $f4, $f2
0x54 0x85 0x21 0x48 # CHECK: luxc1 $f4, $4($5)
0x54 0x85 0x21 0x88 # CHECK: suxc1 $f4, $4($5)

6
test/MC/Mips/micromips-fpu-instructions.s
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@ -25,8 +25,6 @@
# CHECK-EL: nop # encoding: [0x00,0x00,0x00,0x00]
# CHECK-EL: bc1t 1332 # encoding: [0xa0,0x43,0x9a,0x02]
# CHECK-EL: nop # encoding: [0x00,0x00,0x00,0x00]
# CHECK-EL: luxc1 $f2, $4($6) # encoding: [0x86,0x54,0x48,0x11]
# CHECK-EL: suxc1 $f2, $4($6) # encoding: [0x86,0x54,0x88,0x11]
# CHECK-EL: ceil.w.s $f6, $f8 # encoding: [0xc8,0x54,0x3b,0x1b]
# CHECK-EL: ceil.w.d $f6, $f8 # encoding: [0xc8,0x54,0x3b,0x5b]
# CHECK-EL: cvt.w.s $f6, $f8 # encoding: [0xc8,0x54,0x3b,0x09]
@ -102,8 +100,6 @@
# CHECK-EB: nop # encoding: [0x00,0x00,0x00,0x00]
# CHECK-EB: bc1t 1332 # encoding: [0x43,0xa0,0x02,0x9a]
# CHECK-EB: nop # encoding: [0x00,0x00,0x00,0x00]
# CHECK-EB: luxc1 $f2, $4($6) # encoding: [0x54,0x86,0x11,0x48]
# CHECK-EB: suxc1 $f2, $4($6) # encoding: [0x54,0x86,0x11,0x88]
# CHECK-EB: ceil.w.s $f6, $f8 # encoding: [0x54,0xc8,0x1b,0x3b]
# CHECK-EB: ceil.w.d $f6, $f8 # encoding: [0x54,0xc8,0x5b,0x3b]
# CHECK-EB: cvt.w.s $f6, $f8 # encoding: [0x54,0xc8,0x09,0x3b]
@ -182,8 +178,6 @@
sdc1 $f2, 4($6)
bc1f 1332
bc1t 1332
luxc1 $f2, $4($6)
suxc1 $f2, $4($6)
ceil.w.s $f6, $f8
ceil.w.d $f6, $f8
cvt.w.s $f6, $f8