RPCS3/llvm
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm.git synced 2025-02-09 20:13:35 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

AMDGPU/SI: Fix inst-select-load-smrd.mir on some builds

Browse Source 
Summary:
For some reason instructions are being inserted in the wrong order with some
builds.  I'm not sure why this is happening.

Reviewers: arsenm

Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, tony-tye, tpr, llvm-commits

Differential Revision: https://reviews.llvm.org/D29325

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293639 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard 2017-01-31 15:24:11 +00:00
parent 2563d410c9
commit d925fa77b2
2 changed files with 22 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
View File

@ -84,13 +84,19 @@ bool AMDGPUInstructionSelector::selectG_ADD(MachineInstr &I) const {
DebugLoc DL = I.getDebugLoc();
MachineOperand Lo1(getSubOperand64(I.getOperand(1), AMDGPU::sub0));
MachineOperand Lo2(getSubOperand64(I.getOperand(2), AMDGPU::sub0));
BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_ADD_U32), DstLo)
.add(getSubOperand64(I.getOperand(1), AMDGPU::sub0))
.add(getSubOperand64(I.getOperand(2), AMDGPU::sub0));
.add(Lo1)
.add(Lo2);
MachineOperand Hi1(getSubOperand64(I.getOperand(1), AMDGPU::sub1));
MachineOperand Hi2(getSubOperand64(I.getOperand(2), AMDGPU::sub1));
BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_ADDC_U32), DstHi)
.add(getSubOperand64(I.getOperand(1), AMDGPU::sub1))
.add(getSubOperand64(I.getOperand(2), AMDGPU::sub1));
.add(Hi1)
.add(Hi2);
BuildMI(*BB, &I, DL, TII.get(AMDGPU::REG_SEQUENCE), I.getOperand(0).getReg())
.addReg(DstLo)

24
test/CodeGen/AMDGPU/GlobalISel/inst-select-load-smrd.mir
View File

@ -52,11 +52,11 @@ regBankSelected: true
# SIVI: [[K_LO:%[0-9]+]] = S_MOV_B32 4294967292
# SIVI: [[K_HI:%[0-9]+]] = S_MOV_B32 3
# SIVI: [[K:%[0-9]+]] = REG_SEQUENCE [[K_LO]], 1, [[K_HI]], 2
# SIVI: [[K_SUB0:%[0-9]+]] = COPY [[K]].sub0
# SIVI: [[PTR_LO:%[0-9]+]] = COPY [[PTR]].sub0
# SIVI-DAG: [[K_SUB0:%[0-9]+]] = COPY [[K]].sub0
# SIVI-DAG: [[PTR_LO:%[0-9]+]] = COPY [[PTR]].sub0
# SIVI: [[ADD_PTR_LO:%[0-9]+]] = S_ADD_U32 [[PTR_LO]], [[K_SUB0]]
# SIVI: [[K_SUB1:%[0-9]+]] = COPY [[K]].sub1
# SIVI: [[PTR_HI:%[0-9]+]] = COPY [[PTR]].sub1
# SIVI-DAG: [[K_SUB1:%[0-9]+]] = COPY [[K]].sub1
# SIVI-DAG: [[PTR_HI:%[0-9]+]] = COPY [[PTR]].sub1
# SIVI: [[ADD_PTR_HI:%[0-9]+]] = S_ADDC_U32 [[PTR_HI]], [[K_SUB1]]
# SIVI: [[ADD_PTR:%[0-9]+]] = REG_SEQUENCE [[ADD_PTR_LO]], 1, [[ADD_PTR_HI]], 2
# SIVI: S_LOAD_DWORD_IMM [[ADD_PTR]], 0, 0
@ -66,11 +66,11 @@ regBankSelected: true
# GCN: [[K_LO:%[0-9]+]] = S_MOV_B32 0
# GCN: [[K_HI:%[0-9]+]] = S_MOV_B32 4
# GCN: [[K:%[0-9]+]] = REG_SEQUENCE [[K_LO]], 1, [[K_HI]], 2
# GCN: [[K_SUB0:%[0-9]+]] = COPY [[K]].sub0
# GCN: [[PTR_LO:%[0-9]+]] = COPY [[PTR]].sub0
# GCN-DAG: [[K_SUB0:%[0-9]+]] = COPY [[K]].sub0
# GCN-DAG: [[PTR_LO:%[0-9]+]] = COPY [[PTR]].sub0
# GCN: [[ADD_PTR_LO:%[0-9]+]] = S_ADD_U32 [[PTR_LO]], [[K_SUB0]]
# GCN: [[K_SUB1:%[0-9]+]] = COPY [[K]].sub1
# GCN: [[PTR_HI:%[0-9]+]] = COPY [[PTR]].sub1
# GCN-DAG: [[K_SUB1:%[0-9]+]] = COPY [[K]].sub1
# GCN-DAG: [[PTR_HI:%[0-9]+]] = COPY [[PTR]].sub1
# GCN: [[ADD_PTR_HI:%[0-9]+]] = S_ADDC_U32 [[PTR_HI]], [[K_SUB1]]
# GCN: [[ADD_PTR:%[0-9]+]] = REG_SEQUENCE [[ADD_PTR_LO]], 1, [[ADD_PTR_HI]], 2
# GCN: S_LOAD_DWORD_IMM [[ADD_PTR]], 0, 0
@ -87,11 +87,11 @@ regBankSelected: true
# SIVI: [[K_LO:%[0-9]+]] = S_MOV_B32 0
# SIVI: [[K_HI:%[0-9]+]] = S_MOV_B32 1
# SIVI: [[K:%[0-9]+]] = REG_SEQUENCE [[K_LO]], 1, [[K_HI]], 2
# SIVI: [[K_SUB0:%[0-9]+]] = COPY [[K]].sub0
# SIVI: [[PTR_LO:%[0-9]+]] = COPY [[PTR]].sub0
# SIVI-DAG: [[K_SUB0:%[0-9]+]] = COPY [[K]].sub0
# SIVI-DAG: [[PTR_LO:%[0-9]+]] = COPY [[PTR]].sub0
# SIVI: [[ADD_PTR_LO:%[0-9]+]] = S_ADD_U32 [[PTR_LO]], [[K_SUB0]]
# SIVI: [[K_SUB1:%[0-9]+]] = COPY [[K]].sub1
# SIVI: [[PTR_HI:%[0-9]+]] = COPY [[PTR]].sub1
# SIVI-DAG: [[K_SUB1:%[0-9]+]] = COPY [[K]].sub1
# SIVI-DAG: [[PTR_HI:%[0-9]+]] = COPY [[PTR]].sub1
# SIVI: [[ADD_PTR_HI:%[0-9]+]] = S_ADDC_U32 [[PTR_HI]], [[K_SUB1]]
# SIVI: [[ADD_PTR:%[0-9]+]] = REG_SEQUENCE [[ADD_PTR_LO]], 1, [[ADD_PTR_HI]], 2
# SIVI: S_LOAD_DWORD_IMM [[ADD_PTR]], 0, 0