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[x86 frame lowering] In 32-bit mode, use ESI as the base pointer.

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Previously, we were using EBX, but PIC requires the GOT to be in EBX before 
function calls via PLT GOT pointer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161066 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chad Rosier 2012-07-31 18:29:21 +00:00
parent 521ed460e9
commit d97f3a5ab0
2 changed files with 6 additions and 4 deletions
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6
lib/Target/X86/X86RegisterInfo.cpp
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@ -72,13 +72,15 @@ X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
SlotSize = 8;
StackPtr = X86::RSP;
FramePtr = X86::RBP;
BasePtr = X86::RBX;
} else {
SlotSize = 4;
StackPtr = X86::ESP;
FramePtr = X86::EBP;
BasePtr = X86::EBX;
}
// Use a callee-saved register as the base pointer. These registers must
// not conflict with any ABI requirements. For example, in 32-bit mode PIC
// requires GOT in the EBX register before function calls via PLT GOT pointer.
BasePtr = Is64Bit ? X86::RBX : X86::ESI;
}
/// getCompactUnwindRegNum - This function maps the register to the number for

4
test/CodeGen/X86/force-align-stack-alloca.ll
View File

@ -24,8 +24,8 @@ define i64 @g(i32 %i) nounwind {
; CHECK-NEXT: andl $-32, %esp
; CHECK-NEXT: subl $32, %esp
;
; Now setup the base pointer (%ebx).
; CHECK-NEXT: movl %esp, %ebx
; Now setup the base pointer (%esi).
; CHECK-NEXT: movl %esp, %esi
; CHECK-NOT: {{[^ ,]*}}, %esp
;
; The next adjustment of the stack is due to the alloca.