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MachineModel: Inconsequential TableGen SubtargetEmitter fix.

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Drive by fix. I noticed some missing logic that might bite future
users. This shouldn't affect the final output on currently modeled
targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174142 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Trick 2013-02-01 03:19:54 +00:00
parent 7beee28767
commit d9a4f0cbd2
1 changed files with 15 additions and 1 deletions
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16
utils/TableGen/CodeGenSchedule.cpp
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@ -1380,9 +1380,23 @@ void CodeGenSchedModels::collectProcResources() {
SCI != SCE; ++SCI) {
if (SCI->ItinClassDef)
collectItinProcResources(SCI->ItinClassDef);
else
else {
// This class may have a default ReadWrite list which can be overriden by
// InstRW definitions.
if (!SCI->InstRWs.empty()) {
for (RecIter RWI = SCI->InstRWs.begin(), RWE = SCI->InstRWs.end();
RWI != RWE; ++RWI) {
Record *RWModelDef = (*RWI)->getValueAsDef("SchedModel");
IdxVec ProcIndices(1, getProcModel(RWModelDef).Index);
IdxVec Writes, Reads;
findRWs((*RWI)->getValueAsListOfDefs("OperandReadWrites"),
Writes, Reads);
collectRWResources(Writes, Reads, ProcIndices);
}
}
collectRWResources(SCI->Writes, SCI->Reads, SCI->ProcIndices);
}
}
// Add resources separately defined by each subtarget.
RecVec WRDefs = Records.getAllDerivedDefinitions("WriteRes");
for (RecIter WRI = WRDefs.begin(), WRE = WRDefs.end(); WRI != WRE; ++WRI) {