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[mips] Initial implementation of -mabicalls/-mno-abicalls.
This patch implements the main rules for -mno-abicalls such as reserving $gp, and emitting the correct .option directive. Patch by Matheus Almeida and Toma Tabacu Differential Revision: http://reviews.llvm.org/D4231 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215194 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -57,6 +57,8 @@ def MipsInstrInfo : InstrInfo;
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// Mips Subtarget features //
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//===----------------------------------------------------------------------===//
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def FeatureABICalls : SubtargetFeature<"abicalls", "IsABICalls", "true",
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"SVR4-style position-independent code.">;
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def FeatureGP64Bit : SubtargetFeature<"gp64", "IsGP64bit", "true",
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"General Purpose Registers are 64-bit wide.">;
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def FeatureFP64Bit : SubtargetFeature<"fp64", "IsFP64bit", "true",
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@ -671,9 +671,7 @@ printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
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}
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void MipsAsmPrinter::EmitStartOfAsmFile(Module &M) {
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// TODO: Need to add -mabicalls and -mno-abicalls flags.
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// Currently we assume that -mabicalls is the default.
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bool IsABICalls = true;
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bool IsABICalls = Subtarget->isABICalls();
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if (IsABICalls) {
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getTargetStreamer().emitDirectiveAbiCalls();
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Reloc::Model RM = TM.getRelocationModel();
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@ -149,6 +149,12 @@ getReservedRegs(const MachineFunction &MF) const {
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for (unsigned I = 0; I < array_lengthof(ReservedGPR64); ++I)
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Reserved.set(ReservedGPR64[I]);
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// For mno-abicalls, GP is a program invariant!
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if (!Subtarget.isABICalls()) {
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Reserved.set(Mips::GP);
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Reserved.set(Mips::GP_64);
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}
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if (Subtarget.isFP64bit()) {
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// Reserve all registers in AFGR64.
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for (RegIter Reg = Mips::AFGR64RegClass.begin(),
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@ -107,12 +107,13 @@ MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
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MipsTargetMachine *_TM)
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: MipsGenSubtargetInfo(TT, CPU, FS), MipsArchVersion(Mips32),
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MipsABI(UnknownABI), IsLittle(little), IsSingleFloat(false),
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IsFPXX(false), IsFP64bit(false), UseOddSPReg(true), IsNaN2008bit(false),
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IsGP64bit(false), HasVFPU(false), HasCnMips(false), IsLinux(true),
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HasMips3_32(false), HasMips3_32r2(false), HasMips4_32(false),
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HasMips4_32r2(false), HasMips5_32r2(false), InMips16Mode(false),
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InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false),
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HasDSPR2(false), AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16),
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IsFPXX(false), IsABICalls(true), IsFP64bit(false), UseOddSPReg(true),
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IsNaN2008bit(false), IsGP64bit(false), HasVFPU(false), HasCnMips(false),
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IsLinux(true), HasMips3_32(false), HasMips3_32r2(false),
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HasMips4_32(false), HasMips4_32r2(false), HasMips5_32r2(false),
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InMips16Mode(false), InMips16HardFloat(Mips16HardFloat),
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InMicroMipsMode(false), HasDSP(false), HasDSPR2(false),
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AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16),
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HasMSA(false), TM(_TM), TargetTriple(TT),
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DL(computeDataLayout(initializeSubtargetDependencies(CPU, FS, TM))),
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TSInfo(DL), JITInfo(), InstrInfo(MipsInstrInfo::create(*this)),
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@ -65,6 +65,9 @@ protected:
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// IsFPXX - MIPS O32 modeless ABI.
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bool IsFPXX;
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// IsABICalls - SVR4-style position-independent code.
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bool IsABICalls;
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// IsFP64bit - The target processor has 64-bit floating point registers.
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bool IsFP64bit;
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@ -200,6 +203,7 @@ public:
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bool hasCnMips() const { return HasCnMips; }
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bool isLittle() const { return IsLittle; }
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bool isABICalls() const { return IsABICalls; }
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bool isFPXX() const { return IsFPXX; }
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bool isFP64bit() const { return IsFP64bit; }
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bool useOddSPReg() const { return UseOddSPReg; }
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