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[mips] Initial implementation of -mabicalls/-mno-abicalls.

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This patch implements the main rules for -mno-abicalls such as reserving $gp,
and emitting the correct .option directive.

Patch by Matheus Almeida and Toma Tabacu

Differential Revision: http://reviews.llvm.org/D4231


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215194 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Sanders 2014-08-08 10:01:29 +00:00
parent bbdf1e0432
commit da52aa04d9
5 changed files with 20 additions and 9 deletions
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2
lib/Target/Mips/Mips.td
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@ -57,6 +57,8 @@ def MipsInstrInfo : InstrInfo;
// Mips Subtarget features // // Mips Subtarget features //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def FeatureABICalls : SubtargetFeature<"abicalls", "IsABICalls", "true",
"SVR4-style position-independent code.">;
def FeatureGP64Bit : SubtargetFeature<"gp64", "IsGP64bit", "true", def FeatureGP64Bit : SubtargetFeature<"gp64", "IsGP64bit", "true",
"General Purpose Registers are 64-bit wide.">; "General Purpose Registers are 64-bit wide.">;
def FeatureFP64Bit : SubtargetFeature<"fp64", "IsFP64bit", "true", def FeatureFP64Bit : SubtargetFeature<"fp64", "IsFP64bit", "true",

4
lib/Target/Mips/MipsAsmPrinter.cpp
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@ -671,9 +671,7 @@ printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
} }
void MipsAsmPrinter::EmitStartOfAsmFile(Module &M) { void MipsAsmPrinter::EmitStartOfAsmFile(Module &M) {
// TODO: Need to add -mabicalls and -mno-abicalls flags. bool IsABICalls = Subtarget->isABICalls();
// Currently we assume that -mabicalls is the default.
bool IsABICalls = true;
if (IsABICalls) { if (IsABICalls) {
getTargetStreamer().emitDirectiveAbiCalls(); getTargetStreamer().emitDirectiveAbiCalls();
Reloc::Model RM = TM.getRelocationModel(); Reloc::Model RM = TM.getRelocationModel();

6
lib/Target/Mips/MipsRegisterInfo.cpp
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@ -149,6 +149,12 @@ getReservedRegs(const MachineFunction &MF) const {
for (unsigned I = 0; I < array_lengthof(ReservedGPR64); ++I) for (unsigned I = 0; I < array_lengthof(ReservedGPR64); ++I)
Reserved.set(ReservedGPR64[I]); Reserved.set(ReservedGPR64[I]);
// For mno-abicalls, GP is a program invariant!
if (!Subtarget.isABICalls()) {
Reserved.set(Mips::GP);
Reserved.set(Mips::GP_64);
}
if (Subtarget.isFP64bit()) { if (Subtarget.isFP64bit()) {
// Reserve all registers in AFGR64. // Reserve all registers in AFGR64.
for (RegIter Reg = Mips::AFGR64RegClass.begin(), for (RegIter Reg = Mips::AFGR64RegClass.begin(),

13
lib/Target/Mips/MipsSubtarget.cpp
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@ -107,12 +107,13 @@ MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
MipsTargetMachine *_TM) MipsTargetMachine *_TM)
: MipsGenSubtargetInfo(TT, CPU, FS), MipsArchVersion(Mips32), : MipsGenSubtargetInfo(TT, CPU, FS), MipsArchVersion(Mips32),
MipsABI(UnknownABI), IsLittle(little), IsSingleFloat(false), MipsABI(UnknownABI), IsLittle(little), IsSingleFloat(false),
IsFPXX(false), IsFP64bit(false), UseOddSPReg(true), IsNaN2008bit(false), IsFPXX(false), IsABICalls(true), IsFP64bit(false), UseOddSPReg(true),
IsGP64bit(false), HasVFPU(false), HasCnMips(false), IsLinux(true), IsNaN2008bit(false), IsGP64bit(false), HasVFPU(false), HasCnMips(false),
HasMips3_32(false), HasMips3_32r2(false), HasMips4_32(false), IsLinux(true), HasMips3_32(false), HasMips3_32r2(false),
HasMips4_32r2(false), HasMips5_32r2(false), InMips16Mode(false), HasMips4_32(false), HasMips4_32r2(false), HasMips5_32r2(false),
InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false), InMips16Mode(false), InMips16HardFloat(Mips16HardFloat),
HasDSPR2(false), AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16), InMicroMipsMode(false), HasDSP(false), HasDSPR2(false),
AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16),
HasMSA(false), TM(_TM), TargetTriple(TT), HasMSA(false), TM(_TM), TargetTriple(TT),
DL(computeDataLayout(initializeSubtargetDependencies(CPU, FS, TM))), DL(computeDataLayout(initializeSubtargetDependencies(CPU, FS, TM))),
TSInfo(DL), JITInfo(), InstrInfo(MipsInstrInfo::create(*this)), TSInfo(DL), JITInfo(), InstrInfo(MipsInstrInfo::create(*this)),

4
lib/Target/Mips/MipsSubtarget.h
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@ -65,6 +65,9 @@ protected:
// IsFPXX - MIPS O32 modeless ABI. // IsFPXX - MIPS O32 modeless ABI.
bool IsFPXX; bool IsFPXX;
// IsABICalls - SVR4-style position-independent code.
bool IsABICalls;
// IsFP64bit - The target processor has 64-bit floating point registers. // IsFP64bit - The target processor has 64-bit floating point registers.
bool IsFP64bit; bool IsFP64bit;
@ -200,6 +203,7 @@ public:
bool hasCnMips() const { return HasCnMips; } bool hasCnMips() const { return HasCnMips; }
bool isLittle() const { return IsLittle; } bool isLittle() const { return IsLittle; }
bool isABICalls() const { return IsABICalls; }
bool isFPXX() const { return IsFPXX; } bool isFPXX() const { return IsFPXX; }
bool isFP64bit() const { return IsFP64bit; } bool isFP64bit() const { return IsFP64bit; }
bool useOddSPReg() const { return UseOddSPReg; } bool useOddSPReg() const { return UseOddSPReg; }