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https://github.com/RPCS3/llvm.git
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Revert rL302028 due to accidental line ending changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302038 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Simon Pilgrim
parent
30c3f70068
commit
dad8f545ae
@ -3220,29 +3220,6 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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[IntrNoMem]>;
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}
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//===----------------------------------------------------------------------===//
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// LWP
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let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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def int_x86_llwpcb :
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GCCBuiltin<"__builtin_ia32_llwpcb">,
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Intrinsic<[], [llvm_ptr_ty], []>;
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def int_x86_slwpcb :
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GCCBuiltin<"__builtin_ia32_slwpcb">,
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Intrinsic<[llvm_ptr_ty], [], []>;
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def int_x86_lwpins32 :
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GCCBuiltin<"__builtin_ia32_lwpins32">,
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Intrinsic<[llvm_i8_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
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def int_x86_lwpins64 :
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GCCBuiltin<"__builtin_ia32_lwpins64">,
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Intrinsic<[llvm_i8_ty], [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty], []>;
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def int_x86_lwpval32 :
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GCCBuiltin<"__builtin_ia32_lwpval32">,
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Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
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def int_x86_lwpval64 :
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GCCBuiltin<"__builtin_ia32_lwpval64">,
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Intrinsic<[], [llvm_i64_ty, llvm_i32_ty, llvm_i32_ty], []>;
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}
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//===----------------------------------------------------------------------===//
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// MMX
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2991
lib/Support/Host.cpp
2991
lib/Support/Host.cpp
File diff suppressed because it is too large
Load Diff
@ -170,8 +170,6 @@ def FeatureAES : SubtargetFeature<"aes", "HasAES", "true",
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[FeatureSSE2]>;
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def FeatureTBM : SubtargetFeature<"tbm", "HasTBM", "true",
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"Enable TBM instructions">;
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def FeatureLWP : SubtargetFeature<"lwp", "HasLWP", "true",
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"Enable LWP instructions">;
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def FeatureMOVBE : SubtargetFeature<"movbe", "HasMOVBE", "true",
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"Support MOVBE instruction">;
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def FeatureRDRAND : SubtargetFeature<"rdrnd", "HasRDRAND", "true",
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@ -693,7 +691,6 @@ def : Proc<"bdver1", [
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FeatureLZCNT,
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FeaturePOPCNT,
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FeatureXSAVE,
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FeatureLWP,
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FeatureSlowSHLD,
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FeatureLAHFSAHF
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]>;
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@ -716,7 +713,6 @@ def : Proc<"bdver2", [
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FeatureXSAVE,
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FeatureBMI,
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FeatureTBM,
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FeatureLWP,
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FeatureFMA,
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FeatureSlowSHLD,
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FeatureLAHFSAHF
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@ -741,7 +737,6 @@ def : Proc<"bdver3", [
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FeatureXSAVE,
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FeatureBMI,
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FeatureTBM,
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FeatureLWP,
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FeatureFMA,
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FeatureXSAVEOPT,
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FeatureSlowSHLD,
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@ -768,7 +763,6 @@ def : Proc<"bdver4", [
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FeatureBMI,
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FeatureBMI2,
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FeatureTBM,
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FeatureLWP,
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FeatureFMA,
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FeatureXSAVEOPT,
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FeatureSlowSHLD,
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@ -20318,19 +20318,6 @@ static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget &Subtarget,
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// during ExpandISelPseudos in EmitInstrWithCustomInserter.
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return SDValue();
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}
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case Intrinsic::x86_lwpins32:
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case Intrinsic::x86_lwpins64: {
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SDLoc dl(Op);
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SDValue Chain = Op->getOperand(0);
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SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Other);
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SDValue LwpIns =
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DAG.getNode(X86ISD::LWPINS, dl, VTs, Chain, Op->getOperand(2),
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Op->getOperand(3), Op->getOperand(4));
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SDValue SetCC = getSETCC(X86::COND_B, LwpIns.getValue(0), dl, DAG);
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SDValue Result = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, SetCC);
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return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result,
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LwpIns.getValue(1));
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}
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}
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return SDValue();
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}
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@ -24507,7 +24494,6 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case X86ISD::CVTP2UI_RND: return "X86ISD::CVTP2UI_RND";
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case X86ISD::CVTS2SI_RND: return "X86ISD::CVTS2SI_RND";
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case X86ISD::CVTS2UI_RND: return "X86ISD::CVTS2UI_RND";
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case X86ISD::LWPINS: return "X86ISD::LWPINS";
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}
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return nullptr;
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}
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@ -559,9 +559,6 @@ namespace llvm {
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// Conversions between float and half-float.
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CVTPS2PH, CVTPH2PS,
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// LWP insert record.
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LWPINS,
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// Compare and swap.
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LCMPXCHG_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE,
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LCMPXCHG8_DAG,
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@ -283,11 +283,6 @@ def X86SegAlloca : SDNode<"X86ISD::SEG_ALLOCA", SDT_X86SEG_ALLOCA,
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def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL,
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[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
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def X86lwpins : SDNode<"X86ISD::LWPINS",
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SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisInt<1>,
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SDTCisVT<2, i32>, SDTCisVT<3, i32>]>,
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[SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPSideEffect]>;
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//===----------------------------------------------------------------------===//
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// X86 Operand Definitions.
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//
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@ -841,7 +836,6 @@ def HasFMA : Predicate<"Subtarget->hasFMA()">;
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def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
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def HasXOP : Predicate<"Subtarget->hasXOP()">;
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def HasTBM : Predicate<"Subtarget->hasTBM()">;
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def HasLWP : Predicate<"Subtarget->hasLWP()">;
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def HasMOVBE : Predicate<"Subtarget->hasMOVBE()">;
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def HasRDRAND : Predicate<"Subtarget->hasRDRAND()">;
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def HasF16C : Predicate<"Subtarget->hasF16C()">;
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@ -2449,59 +2443,6 @@ defm T1MSKC : tbm_binary_intr<0x01, "t1mskc", MRM7r, MRM7m>;
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defm TZMSK : tbm_binary_intr<0x01, "tzmsk", MRM4r, MRM4m>;
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} // HasTBM, EFLAGS
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//===----------------------------------------------------------------------===//
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// Lightweight Profiling Instructions
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let Predicates = [HasLWP] in {
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def LLWPCB : I<0x12, MRM0r, (outs), (ins GR32:$src), "llwpcb\t$src",
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[(int_x86_llwpcb GR32:$src)], IIC_LWP>,
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XOP, XOP9, Requires<[Not64BitMode]>;
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def SLWPCB : I<0x12, MRM1r, (outs GR32:$dst), (ins), "slwpcb\t$dst",
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[(set GR32:$dst, (int_x86_slwpcb))], IIC_LWP>,
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XOP, XOP9, Requires<[Not64BitMode]>;
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def LLWPCB64 : I<0x12, MRM0r, (outs), (ins GR64:$src), "llwpcb\t$src",
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[(int_x86_llwpcb GR64:$src)], IIC_LWP>,
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XOP, XOP9, VEX_W, Requires<[In64BitMode]>;
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def SLWPCB64 : I<0x12, MRM1r, (outs GR64:$dst), (ins), "slwpcb\t$dst",
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[(set GR64:$dst, (int_x86_slwpcb))], IIC_LWP>,
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XOP, XOP9, VEX_W, Requires<[In64BitMode]>;
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multiclass lwpins_intr<RegisterClass RC> {
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def rri : Ii32<0x12, MRM0r, (outs), (ins RC:$src0, GR32:$src1, i32imm:$cntl),
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"lwpins\t{$cntl, $src1, $src0|$src0, $src1, $cntl}",
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[(set EFLAGS, (X86lwpins RC:$src0, GR32:$src1, imm:$cntl))]>,
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XOP_4V, XOPA;
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let mayLoad = 1 in
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def rmi : Ii32<0x12, MRM0m, (outs), (ins RC:$src0, i32mem:$src1, i32imm:$cntl),
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"lwpins\t{$cntl, $src1, $src0|$src0, $src1, $cntl}",
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[(set EFLAGS, (X86lwpins RC:$src0, (loadi32 addr:$src1), imm:$cntl))]>,
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XOP_4V, XOPA;
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}
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let Defs = [EFLAGS] in {
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defm LWPINS32 : lwpins_intr<GR32>;
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defm LWPINS64 : lwpins_intr<GR64>, VEX_W;
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} // EFLAGS
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multiclass lwpval_intr<RegisterClass RC, Intrinsic Int> {
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def rri : Ii32<0x12, MRM1r, (outs), (ins RC:$src0, GR32:$src1, i32imm:$cntl),
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"lwpval\t{$cntl, $src1, $src0|$src0, $src1, $cntl}",
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[(Int RC:$src0, GR32:$src1, imm:$cntl)], IIC_LWP>,
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XOP_4V, XOPA;
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let mayLoad = 1 in
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def rmi : Ii32<0x12, MRM1m, (outs), (ins RC:$src0, i32mem:$src1, i32imm:$cntl),
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"lwpval\t{$cntl, $src1, $src0|$src0, $src1, $cntl}",
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[(Int RC:$src0, (loadi32 addr:$src1), imm:$cntl)], IIC_LWP>,
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XOP_4V, XOPA;
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}
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defm LWPVAL32 : lwpval_intr<GR32, int_x86_lwpval32>;
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defm LWPVAL64 : lwpval_intr<GR64, int_x86_lwpval64>, VEX_W;
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} // HasLWP
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//===----------------------------------------------------------------------===//
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// MONITORX/MWAITX Instructions
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//
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File diff suppressed because it is too large
Load Diff
@ -265,7 +265,6 @@ void X86Subtarget::initializeEnvironment() {
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HasFMA4 = false;
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HasXOP = false;
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HasTBM = false;
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HasLWP = false;
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HasMOVBE = false;
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HasRDRAND = false;
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HasF16C = false;
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@ -124,9 +124,6 @@ protected:
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/// Target has TBM instructions.
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bool HasTBM;
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/// Target has LWP instructions
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bool HasLWP;
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/// True if the processor has the MOVBE instruction.
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bool HasMOVBE;
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@ -450,7 +447,6 @@ public:
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bool hasAnyFMA() const { return hasFMA() || hasFMA4(); }
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bool hasXOP() const { return HasXOP; }
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bool hasTBM() const { return HasTBM; }
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bool hasLWP() const { return HasLWP; }
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bool hasMOVBE() const { return HasMOVBE; }
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bool hasRDRAND() const { return HasRDRAND; }
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bool hasF16C() const { return HasF16C; }
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@ -1,49 +0,0 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+lwp | FileCheck %s --check-prefix=X64
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; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=bdver1 | FileCheck %s --check-prefix=X64
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; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=bdver2 | FileCheck %s --check-prefix=X64
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; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=bdver3 | FileCheck %s --check-prefix=X64
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; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=bdver4 | FileCheck %s --check-prefix=X64
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define i8 @test_lwpins64_rri(i64 %a0, i32 %a1) nounwind {
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; X64-LABEL: test_lwpins64_rri:
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; X64: # BB#0:
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; X64-NEXT: lwpins $-1985229329, %esi, %rdi # imm = 0x89ABCDEF
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; X64-NEXT: setb %al
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; X64-NEXT: retq
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%1 = tail call i8 @llvm.x86.lwpins64(i64 %a0, i32 %a1, i32 2309737967)
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ret i8 %1
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}
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define i8 @test_lwpins64_rmi(i64 %a0, i32 *%p1) nounwind {
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; X64-LABEL: test_lwpins64_rmi:
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; X64: # BB#0:
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; X64-NEXT: lwpins $1985229328, (%rsi), %rdi # imm = 0x76543210
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; X64-NEXT: setb %al
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; X64-NEXT: retq
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%a1 = load i32, i32 *%p1
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%1 = tail call i8 @llvm.x86.lwpins64(i64 %a0, i32 %a1, i32 1985229328)
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ret i8 %1
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}
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define void @test_lwpval64_rri(i64 %a0, i32 %a1) nounwind {
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; X64-LABEL: test_lwpval64_rri:
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; X64: # BB#0:
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; X64-NEXT: lwpval $-19088744, %esi, %rdi # imm = 0xFEDCBA98
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; X64-NEXT: retq
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tail call void @llvm.x86.lwpval64(i64 %a0, i32 %a1, i32 4275878552)
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ret void
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}
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define void @test_lwpval64_rmi(i64 %a0, i32 *%p1) nounwind {
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; X64-LABEL: test_lwpval64_rmi:
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; X64: # BB#0:
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; X64-NEXT: lwpval $305419896, (%rsi), %rdi # imm = 0x12345678
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; X64-NEXT: retq
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%a1 = load i32, i32 *%p1
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tail call void @llvm.x86.lwpval64(i64 %a0, i32 %a1, i32 305419896)
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ret void
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}
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declare i8 @llvm.x86.lwpins64(i64, i32, i32) nounwind
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declare void @llvm.x86.lwpval64(i64, i32, i32) nounwind
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@ -1,121 +0,0 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-unknown -mattr=+lwp | FileCheck %s --check-prefix=X86
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; RUN: llc < %s -mtriple=i686-unknown -mcpu=bdver1 | FileCheck %s --check-prefix=X86
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; RUN: llc < %s -mtriple=i686-unknown -mcpu=bdver2 | FileCheck %s --check-prefix=X86
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; RUN: llc < %s -mtriple=i686-unknown -mcpu=bdver3 | FileCheck %s --check-prefix=X86
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; RUN: llc < %s -mtriple=i686-unknown -mcpu=bdver4 | FileCheck %s --check-prefix=X86
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+lwp | FileCheck %s --check-prefix=X64
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; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=bdver1 | FileCheck %s --check-prefix=X64
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; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=bdver2 | FileCheck %s --check-prefix=X64
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; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=bdver3 | FileCheck %s --check-prefix=X64
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; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=bdver4 | FileCheck %s --check-prefix=X64
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define void @test_llwpcb(i8 *%a0) nounwind {
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; X86-LABEL: test_llwpcb:
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; X86: # BB#0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: llwpcb %eax
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; X86-NEXT: retl
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;
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; X64-LABEL: test_llwpcb:
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; X64: # BB#0:
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; X64-NEXT: llwpcb %rdi
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; X64-NEXT: retq
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tail call void @llvm.x86.llwpcb(i8 *%a0)
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ret void
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}
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define i8* @test_slwpcb(i8 *%a0) nounwind {
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; X86-LABEL: test_slwpcb:
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; X86: # BB#0:
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; X86-NEXT: slwpcb %eax
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; X86-NEXT: retl
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;
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; X64-LABEL: test_slwpcb:
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; X64: # BB#0:
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; X64-NEXT: slwpcb %rax
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; X64-NEXT: retq
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%1 = tail call i8* @llvm.x86.slwpcb()
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ret i8 *%1
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}
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define i8 @test_lwpins32_rri(i32 %a0, i32 %a1) nounwind {
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; X86-LABEL: test_lwpins32_rri:
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; X86: # BB#0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: addl %ecx, %ecx
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; X86-NEXT: lwpins $-1985229329, %ecx, %eax # imm = 0x89ABCDEF
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; X86-NEXT: setb %al
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; X86-NEXT: retl
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;
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; X64-LABEL: test_lwpins32_rri:
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; X64: # BB#0:
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; X64-NEXT: addl %esi, %esi
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; X64-NEXT: lwpins $-1985229329, %esi, %edi # imm = 0x89ABCDEF
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; X64-NEXT: setb %al
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; X64-NEXT: retq
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%1 = add i32 %a1, %a1
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%2 = tail call i8 @llvm.x86.lwpins32(i32 %a0, i32 %1, i32 2309737967)
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ret i8 %2
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}
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define i8 @test_lwpins32_rmi(i32 %a0, i32 *%p1) nounwind {
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; X86-LABEL: test_lwpins32_rmi:
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; X86: # BB#0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: lwpins $1985229328, (%eax), %ecx # imm = 0x76543210
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; X86-NEXT: setb %al
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; X86-NEXT: retl
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;
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; X64-LABEL: test_lwpins32_rmi:
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; X64: # BB#0:
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; X64-NEXT: lwpins $1985229328, (%rsi), %edi # imm = 0x76543210
|
||||
; X64-NEXT: setb %al
|
||||
; X64-NEXT: retq
|
||||
%a1 = load i32, i32 *%p1
|
||||
%1 = tail call i8 @llvm.x86.lwpins32(i32 %a0, i32 %a1, i32 1985229328)
|
||||
ret i8 %1
|
||||
}
|
||||
|
||||
define void @test_lwpval32_rri(i32 %a0, i32 %a1) nounwind {
|
||||
; X86-LABEL: test_lwpval32_rri:
|
||||
; X86: # BB#0:
|
||||
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
|
||||
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
|
||||
; X86-NEXT: addl %ecx, %ecx
|
||||
; X86-NEXT: lwpval $-19088744, %ecx, %eax # imm = 0xFEDCBA98
|
||||
; X86-NEXT: retl
|
||||
;
|
||||
; X64-LABEL: test_lwpval32_rri:
|
||||
; X64: # BB#0:
|
||||
; X64-NEXT: addl %esi, %esi
|
||||
; X64-NEXT: lwpval $-19088744, %esi, %edi # imm = 0xFEDCBA98
|
||||
; X64-NEXT: retq
|
||||
%1 = add i32 %a1, %a1
|
||||
tail call void @llvm.x86.lwpval32(i32 %a0, i32 %1, i32 4275878552)
|
||||
ret void
|
||||
}
|
||||
|
||||
define void @test_lwpval32_rmi(i32 %a0, i32 *%p1) nounwind {
|
||||
; X86-LABEL: test_lwpval32_rmi:
|
||||
; X86: # BB#0:
|
||||
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
|
||||
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
|
||||
; X86-NEXT: lwpval $305419896, (%eax), %ecx # imm = 0x12345678
|
||||
; X86-NEXT: retl
|
||||
;
|
||||
; X64-LABEL: test_lwpval32_rmi:
|
||||
; X64: # BB#0:
|
||||
; X64-NEXT: lwpval $305419896, (%rsi), %edi # imm = 0x12345678
|
||||
; X64-NEXT: retq
|
||||
%a1 = load i32, i32 *%p1
|
||||
tail call void @llvm.x86.lwpval32(i32 %a0, i32 %a1, i32 305419896)
|
||||
ret void
|
||||
}
|
||||
|
||||
declare void @llvm.x86.llwpcb(i8*) nounwind
|
||||
declare i8* @llvm.x86.slwpcb() nounwind
|
||||
declare i8 @llvm.x86.lwpins32(i32, i32, i32) nounwind
|
||||
declare void @llvm.x86.lwpval32(i32, i32, i32) nounwind
|
||||
@ -773,21 +773,3 @@
|
||||
|
||||
#CHECK: getsec
|
||||
0x0f 0x37
|
||||
|
||||
#CHECK: llwpcb %ecx
|
||||
0x8f 0xe9 0x78 0x12 0xc1
|
||||
|
||||
#CHECK: slwpcb %ecx
|
||||
0x8f 0xe9 0x78 0x12 0xc9
|
||||
|
||||
# CHECK: lwpins $305419896, %ebx, %eax
|
||||
0x8f 0xea 0x78 0x12 0xc3 0x78 0x56 0x34 0x12
|
||||
|
||||
# CHECK: lwpins $591751049, (%esp), %edx
|
||||
0x8f 0xea 0x68 0x12 0x04 0x24 0x89 0x67 0x45 0x23
|
||||
|
||||
# CHECK: lwpval $1737075661, %ebx, %eax
|
||||
0x8f 0xea 0x78 0x12 0xcb 0xcd 0xab 0x89 0x67
|
||||
|
||||
# CHECK: lwpval $2309737967, (%esp), %edx
|
||||
0x8f 0xea 0x68 0x12 0x0c 0x24 0xef 0xcd 0xab 0x89
|
||||
|
||||
@ -456,27 +456,3 @@
|
||||
|
||||
# CHECK: callq -32769
|
||||
0xe8 0xff 0x7f 0xff 0xff
|
||||
|
||||
# CHECK: llwpcb %rax
|
||||
0x8f 0xe9 0xf8 0x12 0xc0
|
||||
|
||||
# CHECK: slwpcb %rax
|
||||
0x8f 0xe9 0xf8 0x12 0xc8
|
||||
|
||||
# CHECK: lwpins $305419896, %ebx, %rax
|
||||
0x8f 0xea 0xf8 0x12 0xc3 0x78 0x56 0x34 0x12
|
||||
|
||||
# CHECK: lwpins $591751049, (%rsp), %rdx
|
||||
0x8f 0xea 0xe8 0x12 0x04 0x24 0x89 0x67 0x45 0x23
|
||||
|
||||
# CHECK: lwpins $591751049, (%esp), %edx
|
||||
0x67 0x8f 0xea 0x68 0x12 0x04 0x24 0x89 0x67 0x45 0x23
|
||||
|
||||
# CHECK: lwpval $1737075661, %ebx, %rax
|
||||
0x8f 0xea 0xf8 0x12 0xcb 0xcd 0xab 0x89 0x67
|
||||
|
||||
# CHECK: lwpval $2309737967, (%rsp), %rdx
|
||||
0x8f 0xea 0xe8 0x12 0x0c 0x24 0xef 0xcd 0xab 0x89
|
||||
|
||||
# CHECK: lwpval $2309737967, (%esp), %edx
|
||||
0x67 0x8f 0xea 0x68 0x12 0x0c 0x24 0xef 0xcd 0xab 0x89
|
||||
|
||||
@ -1,25 +0,0 @@
|
||||
# RUN: llvm-mc -triple x86_64-unknown-unknown --show-encoding %s | FileCheck %s --check-prefix=CHECK
|
||||
|
||||
llwpcb %rcx
|
||||
# CHECK: llwpcb %rcx
|
||||
# CHECK: encoding: [0x8f,0xe9,0xf8,0x12,0xc1]
|
||||
|
||||
slwpcb %rax
|
||||
# CHECK: slwpcb %rax
|
||||
# CHECK: encoding: [0x8f,0xe9,0xf8,0x12,0xc8]
|
||||
|
||||
lwpins $305419896, %ebx, %rax
|
||||
# CHECK: lwpins $305419896, %ebx, %rax
|
||||
# CHECK: encoding: [0x8f,0xea,0xf8,0x12,0xc3,0x78,0x56,0x34,0x12]
|
||||
|
||||
lwpins $591751049, (%rsp), %rdx
|
||||
# CHECK: lwpins $591751049, (%rsp), %rdx
|
||||
# CHECK: encoding: [0x8f,0xea,0xe8,0x12,0x04,0x24,0x89,0x67,0x45,0x23]
|
||||
|
||||
lwpval $1737075661, %ebx, %rax
|
||||
# CHECK: lwpval $1737075661, %ebx, %rax
|
||||
# CHECK: encoding: [0x8f,0xea,0xf8,0x12,0xcb,0xcd,0xab,0x89,0x67]
|
||||
|
||||
lwpval $2309737967, (%rsp), %rdx
|
||||
# CHECK: lwpval $2309737967, (%rsp), %rdx
|
||||
# CHECK: encoding: [0x8f,0xea,0xe8,0x12,0x0c,0x24,0xef,0xcd,0xab,0x89]
|
||||
@ -1,32 +0,0 @@
|
||||
# RUN: llvm-mc -triple i686-unknown-unknown --show-encoding %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-X86
|
||||
# RUN: llvm-mc -triple x86_64-unknown-unknown --show-encoding %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-X64
|
||||
|
||||
llwpcb %ecx
|
||||
# CHECK: llwpcb %ecx
|
||||
# CHECK-X86: encoding: [0x8f,0xe9,0x78,0x12,0xc1]
|
||||
# CHECK-X64: encoding: [0x8f,0xe9,0x78,0x12,0xc1]
|
||||
|
||||
slwpcb %eax
|
||||
# CHECK: slwpcb %eax
|
||||
# CHECK-X86: encoding: [0x8f,0xe9,0x78,0x12,0xc8]
|
||||
# CHECK-X64: encoding: [0x8f,0xe9,0x78,0x12,0xc8]
|
||||
|
||||
lwpins $305419896, %ebx, %eax
|
||||
# CHECK: lwpins $305419896, %ebx, %eax
|
||||
# CHECK-X86: encoding: [0x8f,0xea,0x78,0x12,0xc3,0x78,0x56,0x34,0x12]
|
||||
# CHECK-X64: encoding: [0x8f,0xea,0x78,0x12,0xc3,0x78,0x56,0x34,0x12]
|
||||
|
||||
lwpins $591751049, (%esp), %edx
|
||||
# CHECK: lwpins $591751049, (%esp), %edx
|
||||
# CHECK-X86: encoding: [0x8f,0xea,0x68,0x12,0x04,0x24,0x89,0x67,0x45,0x23]
|
||||
# CHECK-X64: encoding: [0x67,0x8f,0xea,0x68,0x12,0x04,0x24,0x89,0x67,0x45,0x23]
|
||||
|
||||
lwpval $1737075661, %ebx, %eax
|
||||
# CHECK: lwpval $1737075661, %ebx, %eax
|
||||
# CHECK-X86: encoding: [0x8f,0xea,0x78,0x12,0xcb,0xcd,0xab,0x89,0x67]
|
||||
# CHECK-X64: encoding: [0x8f,0xea,0x78,0x12,0xcb,0xcd,0xab,0x89,0x67]
|
||||
|
||||
lwpval $2309737967, (%esp), %edx
|
||||
# CHECK: lwpval $2309737967, (%esp), %edx
|
||||
# CHECK-X86: encoding: [0x8f,0xea,0x68,0x12,0x0c,0x24,0xef,0xcd,0xab,0x89]
|
||||
# CHECK-X64: encoding: [0x67,0x8f,0xea,0x68,0x12,0x0c,0x24,0xef,0xcd,0xab,0x89]
|
||||
Loading…
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Reference in New Issue
Block a user