RPCS3/llvm
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm.git synced 2025-01-03 10:19:25 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Recognize inline asm for bswap on x86-64 GLIBC. This allows it

Browse Source 
to be supported in the JIT.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62730 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman 2009-01-21 23:40:54 +00:00
parent c03c46a6af
commit dbf5f2557e
1 changed files with 11 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
lib/Target/X86/X86TargetAsmInfo.cpp
View File

@ -411,11 +411,21 @@ bool X86TargetAsmInfo<BaseTAI>::ExpandInlineAsm(CallInst *CI) const {
// bswap $0 // bswap $0
if (AsmPieces.size() == 2 && if (AsmPieces.size() == 2 &&
AsmPieces[0] == "bswap" && AsmPieces[1] == "$0") { AsmPieces[0] == "bswap" && (AsmPieces[1] == "$0" ||
AsmPieces[1] == "${0:q}")) {
// No need to check constraints, nothing other than the equivalent of // No need to check constraints, nothing other than the equivalent of
// "=r,0" would be valid here. // "=r,0" would be valid here.
return LowerToBSwap(CI); return LowerToBSwap(CI);
} }
// rorw $$8, ${0:w} --> llvm.bswap.i16
if (CI->getType() == Type::Int16Ty &&
AsmPieces.size() == 3 &&
AsmPieces[0] == "rorw" &&
AsmPieces[1] == "$$8," &&
AsmPieces[2] == "${0:w}" &&
IA->getConstraintString() == "=r,0,~{dirflag},~{fpsr},~{flags},~{cc}") {
return LowerToBSwap(CI);
}
break; break;
case 3: case 3:
if (CI->getType() == Type::Int64Ty && Constraints.size() >= 2 && if (CI->getType() == Type::Int64Ty && Constraints.size() >= 2 &&