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Fix some tablegen issues to allow using zero_reg for InstAlias definitions.

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This is needed to allow an InstAlias for an instruction with an "OptionalDef"
result register (like ARM's cc_out) where you want to set the optional register
to reg0.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123490 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson 2011-01-14 22:58:09 +00:00
parent 7cefd0e9d5
commit dc1a2bd3aa
2 changed files with 23 additions and 3 deletions
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11
utils/TableGen/AsmMatcherEmitter.cpp
View File

@ -1380,9 +1380,14 @@ static void EmitConvertToMCInst(CodeGenTarget &Target,
break;
}
case MatchableInfo::ResOperand::RegOperand: {
std::string N = getQualifiedName(OpInfo.Register);
CaseOS << " Inst.addOperand(MCOperand::CreateReg(" << N << "));\n";
Signature += "__reg" + OpInfo.Register->getName();
if (OpInfo.Register == 0) {
CaseOS << " Inst.addOperand(MCOperand::CreateReg(0));\n";
Signature += "__reg0";
} else {
std::string N = getQualifiedName(OpInfo.Register);
CaseOS << " Inst.addOperand(MCOperand::CreateReg(" << N << "));\n";
Signature += "__reg" + OpInfo.Register->getName();
}
}
}
}

15
utils/TableGen/CodeGenInstruction.cpp
View File

@ -442,6 +442,21 @@ CodeGenInstAlias::CodeGenInstAlias(Record *R, CodeGenTarget &T) : TheDef(R) {
++AliasOpNo;
continue;
}
if (ADI->getDef()->getName() == "zero_reg") {
if (!Result->getArgName(AliasOpNo).empty())
throw TGError(R->getLoc(), "result fixed register argument must "
"not have a name!");
// Check if this is an optional def.
if (!ResultOpRec->isSubClassOf("OptionalDefOperand"))
throw TGError(R->getLoc(), "reg0 used for result that is not an "
"OptionalDefOperand!");
// Now that it is validated, add it.
ResultOperands.push_back(ResultOperand(static_cast<Record*>(0)));
++AliasOpNo;
continue;
}
}
// If the operand is a record, it must have a name, and the record type must