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Make sure the X86 backend doesn't explode on 128-bit shuffles in AVX mode. Fixes PR11102.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141585 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eli Friedman 2011-10-10 22:28:47 +00:00
parent e2f2f07be7
commit dca62d53b7
2 changed files with 14 additions and 12 deletions
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16
lib/Target/X86/X86ISelLowering.cpp
View File

@ -3757,12 +3757,8 @@ static bool isVPERMILPDMask(const SmallVectorImpl<int> &Mask, EVT VT,
if (!Subtarget->hasAVX())
return false;
// Match any permutation of 128-bit vector with 64-bit types
if (NumLanes == 1 && NumElts != 2)
return false;
// Only match 256-bit with 32 types
if (VT.getSizeInBits() == 256 && NumElts != 4)
// Only match 256-bit with 64-bit types
if (VT.getSizeInBits() != 256 || NumElts != 4)
return false;
// The mask on the high lane is independent of the low. Both can match
@ -3793,12 +3789,8 @@ static bool isVPERMILPSMask(const SmallVectorImpl<int> &Mask, EVT VT,
if (!Subtarget->hasAVX())
return false;
// Match any permutation of 128-bit vector with 32-bit types
if (NumLanes == 1 && NumElts != 4)
return false;
// Only match 256-bit with 32 types
if (VT.getSizeInBits() == 256 && NumElts != 8)
// Only match 256-bit with 32-bit types
if (VT.getSizeInBits() != 256 || NumElts != 8)
return false;
// The mask on the high lane should be the same as the low. Actually,

10
test/CodeGen/X86/avx-shuffle.ll Normal file
View File

@ -0,0 +1,10 @@
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s
; PR11102
define <4 x float> @test1(<4 x float> %a) nounwind {
%b = shufflevector <4 x float> zeroinitializer, <4 x float> %a, <4 x i32> <i32 2, i32 5, i32 undef, i32 undef>
ret <4 x float> %b
; CHECK: test1:
; CHECK: vshufps
; CHECK: vpshufd
}