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Refactor: Simplify boolean expressions in AArch64 target

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Simplify boolean expressions using `true` and `false` with `clang-tidy`

Patch by Richard Thomson.

Reviewed By: rengolin

Differential Revision: http://reviews.llvm.org/D8525

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233089 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
David Blaikie 2015-03-24 16:24:01 +00:00
parent 06426f54cb
commit dcd8c45f20
2 changed files with 3 additions and 3 deletions
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2
lib/Target/AArch64/AArch64FastISel.cpp
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@ -4563,7 +4563,7 @@ bool AArch64FastISel::selectShift(const Instruction *I) {
unsigned ResultReg = 0; unsigned ResultReg = 0;
uint64_t ShiftVal = C->getZExtValue(); uint64_t ShiftVal = C->getZExtValue();
MVT SrcVT = RetVT; MVT SrcVT = RetVT;
bool IsZExt = (I->getOpcode() == Instruction::AShr) ? false : true; bool IsZExt = I->getOpcode() != Instruction::AShr;
const Value *Op0 = I->getOperand(0); const Value *Op0 = I->getOperand(0);
if (const auto *ZExt = dyn_cast<ZExtInst>(Op0)) { if (const auto *ZExt = dyn_cast<ZExtInst>(Op0)) {
if (!isIntExtFree(ZExt)) { if (!isIntExtFree(ZExt)) {

4
lib/Target/AArch64/AArch64ISelLowering.cpp
View File

@ -1257,7 +1257,7 @@ getAArch64XALUOOp(AArch64CC::CondCode &CC, SDValue Op, SelectionDAG &DAG) {
case ISD::SMULO: case ISD::SMULO:
case ISD::UMULO: { case ISD::UMULO: {
CC = AArch64CC::NE; CC = AArch64CC::NE;
bool IsSigned = (Op.getOpcode() == ISD::SMULO) ? true : false; bool IsSigned = Op.getOpcode() == ISD::SMULO;
if (Op.getValueType() == MVT::i32) { if (Op.getValueType() == MVT::i32) {
unsigned ExtendOpc = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; unsigned ExtendOpc = IsSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
// For a 32 bit multiply with overflow check we want the instruction // For a 32 bit multiply with overflow check we want the instruction
@ -6748,7 +6748,7 @@ bool AArch64TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
unsigned LZ = countLeadingZeros((uint64_t)Val); unsigned LZ = countLeadingZeros((uint64_t)Val);
unsigned Shift = (63 - LZ) / 16; unsigned Shift = (63 - LZ) / 16;
// MOVZ is free so return true for one or fewer MOVK. // MOVZ is free so return true for one or fewer MOVK.
return (Shift < 3) ? true : false; return Shift < 3;
} }
// Generate SUBS and CSEL for integer abs. // Generate SUBS and CSEL for integer abs.