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R600/SI: Cleanup parsing of register names.

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Try to figure out the class and number of subregisters.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206334 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault 2014-04-15 22:32:42 +00:00
parent 569e5a5b1c
commit dd368a8755
2 changed files with 46 additions and 33 deletions
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73
lib/Target/R600/InstPrinter/AMDGPUInstPrinter.cpp
View File

@ -41,43 +41,56 @@ void AMDGPUInstPrinter::printRegOperand(unsigned reg, raw_ostream &O) {
break;
}
// It's seems there's no way to use SIRegisterInfo here, and dealing with the
// giant enum of all the different shifted sets of registers is pretty
// unmanagable, so parse the name and reformat it to be prettier.
StringRef Name(getRegisterName(reg));
char Type;
unsigned NumRegs;
std::pair<StringRef, StringRef> Split = Name.split('_');
StringRef SubRegName = Split.first;
StringRef Rest = Split.second;
if (SubRegName.size() <= 4) { // Must at least be as long as "SGPR"/"VGPR".
O << Name;
if (MRI.getRegClass(AMDGPU::VGPR_32RegClassID).contains(reg)) {
Type = 'v';
NumRegs = 1;
} else if (MRI.getRegClass(AMDGPU::SGPR_32RegClassID).contains(reg)) {
Type = 's';
NumRegs = 1;
} else if (MRI.getRegClass(AMDGPU::VReg_64RegClassID).contains(reg)) {
Type = 'v';
NumRegs = 2;
} else if (MRI.getRegClass(AMDGPU::SReg_64RegClassID).contains(reg)) {
Type = 's';
NumRegs = 2;
} else if (MRI.getRegClass(AMDGPU::VReg_128RegClassID).contains(reg)) {
Type = 'v';
NumRegs = 4;
} else if (MRI.getRegClass(AMDGPU::SReg_128RegClassID).contains(reg)) {
Type = 's';
NumRegs = 4;
} else if (MRI.getRegClass(AMDGPU::VReg_96RegClassID).contains(reg)) {
Type = 'v';
NumRegs = 3;
} else if (MRI.getRegClass(AMDGPU::VReg_256RegClassID).contains(reg)) {
Type = 'v';
NumRegs = 8;
} else if (MRI.getRegClass(AMDGPU::SReg_256RegClassID).contains(reg)) {
Type = 's';
NumRegs = 8;
} else if (MRI.getRegClass(AMDGPU::VReg_512RegClassID).contains(reg)) {
Type = 'v';
NumRegs = 16;
} else if (MRI.getRegClass(AMDGPU::SReg_512RegClassID).contains(reg)) {
Type = 's';
NumRegs = 16;
} else {
O << getRegisterName(reg);
return;
}
unsigned RegIndex;
StringRef RegIndexStr = SubRegName.drop_front(4);
if (RegIndexStr.getAsInteger(10, RegIndex)) {
O << Name;
// The low 8 bits encoding value is the register index, for both VGPRs and
// SGPRs.
unsigned RegIdx = MRI.getEncodingValue(reg) & ((1 << 8) - 1);
if (NumRegs == 1) {
O << Type << RegIdx;
return;
}
if (SubRegName.front() == 'V')
O << 'v';
else if (SubRegName.front() == 'S')
O << 's';
else {
O << Name;
return;
}
if (Rest.empty()) // Only 1 32-bit register
O << RegIndex;
else {
unsigned NumReg = Rest.count('_') + 2;
O << '[' << RegIndex << ':' << (RegIndex + NumReg - 1) << ']';
}
O << Type << '[' << RegIdx << ':' << (RegIdx + NumRegs - 1) << ']';
}
void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,

6
lib/Target/R600/InstPrinter/AMDGPUInstPrinter.h
View File

@ -32,10 +32,10 @@ public:
virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot);
private:
static void printRegOperand(unsigned RegNo, raw_ostream &O);
static void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printRegOperand(unsigned RegNo, raw_ostream &O);
void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
static void printInterpSlot(const MCInst *MI, unsigned OpNum, raw_ostream &O);
static void printMemOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printMemOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
static void printIfSet(const MCInst *MI, unsigned OpNo, raw_ostream &O,
StringRef Asm, StringRef Default = "");
static void printAbs(const MCInst *MI, unsigned OpNo, raw_ostream &O);