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[ARM GlobalISel] Support G_CTLZ for Thumb2

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Same as ARM mode but with different opcode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355191 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Diana Picus 2019-03-01 10:12:28 +00:00
parent 6535445674
commit de23a6b25f
3 changed files with 34 additions and 7 deletions
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7
lib/Target/ARM/ARMLegalizerInfo.cpp
View File

@ -206,13 +206,6 @@ ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) {
getActionDefinitionsBuilder({G_FREM, G_FPOW}).libcallFor({s32, s64});
if (ST.isThumb()) {
// FIXME: merge with the code for non-Thumb.
computeTables();
verify(*ST.getInstrInfo());
return;
}
if (ST.hasV5TOps()) {
getActionDefinitionsBuilder(G_CTLZ)
.legalFor({s32, s32})

1
test/CodeGen/ARM/GlobalISel/arm-legalize-bitcounts.mir
View File

@ -1,4 +1,5 @@
# RUN: llc -O0 -mtriple arm-linux-gnueabi -mattr=+v5t -run-pass=legalizer %s -o - | FileCheck %s -check-prefixes=CHECK,CLZ
# RUN: llc -O0 -mtriple thumb-linux-gnueabi -mattr=+v6t2 -run-pass=legalizer %s -o - | FileCheck %s -check-prefixes=CHECK,CLZ
# RUN: llc -O0 -mtriple arm-linux-gnueabi -mattr=-v5t -run-pass=legalizer %s -o - | FileCheck %s -check-prefixes=CHECK,LIBCALLS
--- |
define void @test_ctlz_s32() { ret void }

33
test/CodeGen/ARM/GlobalISel/select-clz.mir Normal file
View File

@ -0,0 +1,33 @@
# RUN: llc -O0 -mtriple arm-- -mattr=+v6 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,ARM
# RUN: llc -O0 -mtriple thumb-- -mattr=+v6t2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,THUMB
--- |
define void @test_clz() { ret void }
...
---
name: test_clz
# CHECK-LABEL: name: test_clz
legalized: true
regBankSelected: true
selected: false
# CHECK: selected: true
registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
body: |
bb.0:
liveins: $r0
%0(s32) = COPY $r0
; ARM: [[VREGX:%[0-9]+]]:gpr = COPY $r0
; THUMB: [[VREGX:%[0-9]+]]:rgpr = COPY $r0
%1(s32) = G_CTLZ %0(s32)
; ARM: [[VREGR:%[0-9]+]]:gpr = CLZ [[VREGX]], 14, $noreg
; THUMB: [[VREGR:%[0-9]+]]:rgpr = t2CLZ [[VREGX]], 14, $noreg
$r0 = COPY %1(s32)
; CHECK: $r0 = COPY [[VREGR]]
BX_RET 14, $noreg, implicit $r0
; CHECK: BX_RET 14, $noreg, implicit $r0
...