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Adding support for instructions mfc0, mfc2, mtc0, mtc2

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move from and to coprocessors 0 and 2.

Contributer: Vladimir Medic


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165351 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jack Carter 2012-10-06 01:17:37 +00:00
parent 2490dc6508
commit de33227462
3 changed files with 54 additions and 0 deletions
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21
lib/Target/Mips/MipsInstrFormats.td
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@ -171,6 +171,27 @@ class FJ<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
let Inst{25-0} = addr;
}
//===----------------------------------------------------------------------===//
// MFC instruction class in Mips : <|op|mf|rt|rd|0000000|sel|>
//===----------------------------------------------------------------------===//
class MFC3OP<bits<6> op, bits<5> _mfmt, dag outs, dag ins, string asmstr>:
InstSE<outs, ins, asmstr, [], NoItinerary, FrmFR>
{
bits<5> mfmt;
bits<5> rt;
bits<5> rd;
bits<3> sel;
let Opcode = op;
let mfmt = _mfmt;
let Inst{25-21} = mfmt;
let Inst{20-16} = rt;
let Inst{15-11} = rd;
let Inst{10-3} = 0;
let Inst{2-0} = sel;
}
//===----------------------------------------------------------------------===//
//
// FLOATING POINT INSTRUCTION FORMATS

17
lib/Target/Mips/MipsInstrInfo.td
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@ -296,6 +296,23 @@ def addr :
// Instructions specific format
//===----------------------------------------------------------------------===//
/// Move Control Registers From/To CPU Registers
def MFC0_3OP : MFC3OP<0x10, 0, (outs CPURegs:$rt),
(ins CPURegs:$rd, uimm16:$sel),"mfc0\t$rt, $rd, $sel">;
def : InstAlias<"mfc0 $rt, $rd", (MFC0_3OP CPURegs:$rt, CPURegs:$rd, 0)>;
def MTC0_3OP : MFC3OP<0x10, 4, (outs CPURegs:$rd, uimm16:$sel),
(ins CPURegs:$rt),"mtc0\t$rt, $rd, $sel">;
def : InstAlias<"mtc0 $rt, $rd", (MTC0_3OP CPURegs:$rd, 0, CPURegs:$rt)>;
def MFC2_3OP : MFC3OP<0x12, 0, (outs CPURegs:$rt),
(ins CPURegs:$rd, uimm16:$sel),"mfc2\t$rt, $rd, $sel">;
def : InstAlias<"mfc2 $rt, $rd", (MFC2_3OP CPURegs:$rt, CPURegs:$rd, 0)>;
def MTC2_3OP : MFC3OP<0x12, 4, (outs CPURegs:$rd, uimm16:$sel),
(ins CPURegs:$rt),"mtc2\t$rt, $rd, $sel">;
def : InstAlias<"mtc2 $rt, $rd", (MTC2_3OP CPURegs:$rd, 0, CPURegs:$rt)>;
// Arithmetic and logical instructions with 3 register operands.
class ArithLogicR<bits<6> op, bits<6> func, string instr_asm, SDNode OpNode,
InstrItinClass itin, RegisterClass RC, bit isComm = 0>:

16
test/MC/Mips/mips-fpu-instructions.s
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@ -149,6 +149,14 @@
# CHECK: mthi $7 # encoding: [0x11,0x00,0xe0,0x00]
# CHECK: mtlo $7 # encoding: [0x13,0x00,0xe0,0x00]
# CHECK: swc1 $f9, 9158($7) # encoding: [0xc6,0x23,0xe9,0xe4]
# CHECK: mfc0 $6, $7, 0 # encoding: [0x00,0x38,0x06,0x40]
# CHECK: mtc0 $9, $8, 0 # encoding: [0x00,0x40,0x89,0x40]
# CHECK: mfc2 $5, $7, 0 # encoding: [0x00,0x38,0x05,0x48]
# CHECK: mtc2 $9, $4, 0 # encoding: [0x00,0x20,0x89,0x48]
# CHECK: mfc0 $6, $7, 2 # encoding: [0x02,0x38,0x06,0x40]
# CHECK: mtc0 $9, $8, 3 # encoding: [0x03,0x40,0x89,0x40]
# CHECK: mfc2 $5, $7, 4 # encoding: [0x04,0x38,0x05,0x48]
# CHECK: mtc2 $9, $4, 5 # encoding: [0x05,0x20,0x89,0x48]
cfc1 $a2,$0
mfc1 $a2,$f7
@ -160,3 +168,11 @@
mthi $a3
mtlo $a3
swc1 $f9,9158($a3)
mfc0 $6, $7
mtc0 $9, $8
mfc2 $5, $7
mtc2 $9, $4
mfc0 $6, $7, 2
mtc0 $9, $8, 3
mfc2 $5, $7, 4
mtc2 $9, $4, 5