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[CodeGenPrepare] Test case for the promotions that bypass the
profitability check due to some other checks in the addressing mode matcher. I.e., test case for commit r201121. <rdar://problem/16020230> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201132 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -252,3 +252,52 @@ define i8 @twoArgsNoPromotionRemove(i1 %arg1, i8 %arg2, i8* %base) {
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%res = load i8* %arrayidx
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ret i8 %res
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}
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; Ensure that when the profitability checks kicks in, the IR is not modified
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; will IgnoreProfitability is on.
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; The profitabily check happens when a candidate instruction has several uses.
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; The matcher will create a new matcher for each use and check if the
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; instruction is in the list of the matched instructions of this new matcher.
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; All changes made by the new matchers must be dropped before pursuing
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; otherwise the state of the original matcher will be wrong.
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;
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; Without the profitability check, when checking for the second use of
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; arrayidx, the matcher promotes everything all the way to %arg1, %arg2.
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; Check that we did not promote anything in the final matching.
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;
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; <rdar://problem/16020230>
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; CHECK-LABEL: @checkProfitability
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; CHECK-NOT: {{%[a-zA-Z_0-9-]+}} = sext i32 %arg1 to i64
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; CHECK-NOT: {{%[a-zA-Z_0-9-]+}} = sext i32 %arg2 to i64
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; CHECK: [[SHL:%[a-zA-Z_0-9-]+]] = shl nsw i32 %arg1, 1
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; CHECK: [[ADD:%[a-zA-Z_0-9-]+]] = add nsw i32 [[SHL]], %arg2
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; CHECK: [[SEXTADD:%[a-zA-Z_0-9-]+]] = sext i32 [[ADD]] to i64
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; BB then
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; CHECK: [[BASE1:%[a-zA-Z_0-9-]+]] = add i64 [[SEXTADD]], 48
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; CHECK: [[ADDR1:%[a-zA-Z_0-9-]+]] = inttoptr i64 [[BASE1]] to i32*
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; CHECK: load i32* [[ADDR1]]
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; BB else
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; CHECK: [[BASE2:%[a-zA-Z_0-9-]+]] = add i64 [[SEXTADD]], 48
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; CHECK: [[ADDR2:%[a-zA-Z_0-9-]+]] = inttoptr i64 [[BASE2]] to i32*
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; CHECK: load i32* [[ADDR2]]
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; CHECK: ret
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define i32 @checkProfitability(i32 %arg1, i32 %arg2, i1 %test) {
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%shl = shl nsw i32 %arg1, 1
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%add1 = add nsw i32 %shl, %arg2
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%sextidx1 = sext i32 %add1 to i64
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%tmpptr = inttoptr i64 %sextidx1 to i32*
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%arrayidx1 = getelementptr i32* %tmpptr, i64 12
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br i1 %test, label %then, label %else
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then:
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%res1 = load i32* %arrayidx1
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br label %end
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else:
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%res2 = load i32* %arrayidx1
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br label %end
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end:
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%tmp = phi i32 [%res1, %then], [%res2, %else]
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%res = add i32 %tmp, %add1
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%addr = inttoptr i32 %res to i32*
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%final = load i32* %addr
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ret i32 %final
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}
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