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gcc lower SSE prefetch into generic prefetch intrinsic. Need to add support

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later.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27591 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2006-04-11 18:04:57 +00:00
parent 135c6a9d83
commit df3c33c57e
2 changed files with 4 additions and 11 deletions
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3
include/llvm/IntrinsicsX86.td
View File

@ -139,9 +139,6 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
// Cacheability support ops
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_sse_prefetch : GCCBuiltin<"__builtin_ia32_prefetch">,
Intrinsic<[llvm_void_ty, llvm_ptr_ty,
llvm_int_ty], [IntrWriteMem]>;
def int_x86_sse_movnt_ps : GCCBuiltin<"__builtin_ia32_movntps">,
Intrinsic<[llvm_void_ty, llvm_ptr_ty,
llvm_v4f32_ty], [IntrWriteMem]>;

12
lib/Target/X86/X86InstrSSE.td
View File

@ -1517,17 +1517,13 @@ def MASKMOVDQU : PDI<0xF7, RawFrm, (ops VR128:$src, VR128:$mask),
// Prefetching loads
def PREFETCHT0 : PSI<0x18, MRM1m, (ops i8mem:$src),
"prefetcht0 $src",
[(int_x86_sse_prefetch addr:$src, 1)]>;
"prefetcht0 $src", []>;
def PREFETCHT1 : PSI<0x18, MRM2m, (ops i8mem:$src),
"prefetcht1 $src",
[(int_x86_sse_prefetch addr:$src, 2)]>;
"prefetcht1 $src", []>;
def PREFETCHT2 : PSI<0x18, MRM3m, (ops i8mem:$src),
"prefetcht2 $src",
[(int_x86_sse_prefetch addr:$src, 3)]>;
"prefetcht2 $src", []>;
def PREFETCHTNTA : PSI<0x18, MRM0m, (ops i8mem:$src),
"prefetchtnta $src",
[(int_x86_sse_prefetch addr:$src, 0)]>;
"prefetchtnta $src", []>;
// Non-temporal stores
def MOVNTPSmr : PSI<0x2B, MRMDestMem, (ops i128mem:$dst, VR128:$src),