RPCS3/llvm
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm.git synced 2025-02-02 00:35:27 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity

Use enums instead of literals in the ARM backend.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104573 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2010-05-25 00:15:15 +00:00
parent ef473bfc44
commit e00fa64c16
2 changed files with 18 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

32
lib/Target/ARM/ARMBaseRegisterInfo.cpp
View File

@ -259,10 +259,10 @@ ARMBaseRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
unsigned SubIdx) const {
switch (SubIdx) {
default: return 0;
case 1:
case 2:
case 3:
case 4: {
case ARM::ssub_0:
case ARM::ssub_1:
case ARM::ssub_2:
case ARM::ssub_3: {
// S sub-registers.
if (A->getSize() == 8) {
if (B == &ARM::SPR_8RegClass)
@ -288,10 +288,10 @@ ARMBaseRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
return 0; // Do not allow coalescing!
}
case 5:
case 6:
case 7:
case 8: {
case ARM::dsub_0:
case ARM::dsub_1:
case ARM::dsub_2:
case ARM::dsub_3: {
// D sub-registers.
if (A->getSize() == 16) {
if (B == &ARM::DPR_VFP2RegClass)
@ -314,18 +314,18 @@ ARMBaseRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
return 0; // Do not allow coalescing!
return A;
}
case 9:
case 10:
case 11:
case 12: {
case ARM::dsub_4:
case ARM::dsub_5:
case ARM::dsub_6:
case ARM::dsub_7: {
// D sub-registers of QQQQ registers.
if (A->getSize() == 64 && B == &ARM::DPRRegClass)
return A;
return 0; // Do not allow coalescing!
}
case 13:
case 14: {
case ARM::qsub_0:
case ARM::qsub_1: {
// Q sub-registers.
if (A->getSize() == 32) {
if (B == &ARM::QPR_VFP2RegClass)
@ -340,8 +340,8 @@ ARMBaseRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
return A;
return 0; // Do not allow coalescing!
}
case 15:
case 16: {
case ARM::qsub_2:
case ARM::qsub_3: {
// Q sub-registers of QQQQ registers.
if (A->getSize() == 64 && B == &ARM::QPRRegClass)
return A;

4
lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
View File

@ -327,8 +327,8 @@ void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
} else if (Modifier && strcmp(Modifier, "lane") == 0) {
unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(Reg);
unsigned DReg =
TM.getRegisterInfo()->getMatchingSuperReg(Reg, RegNum & 1 ? 2 : 1,
&ARM::DPR_VFP2RegClass);
TM.getRegisterInfo()->getMatchingSuperReg(Reg,
RegNum & 1 ? ARM::ssub_1 : ARM::ssub_0, &ARM::DPR_VFP2RegClass);
O << getRegisterName(DReg) << '[' << (RegNum & 1) << ']';
} else {
assert(!MO.getSubReg() && "Subregs should be eliminated!");