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[AVX512] Fix VSQRT packed instructions internal names.
No functional change git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220808 91177308-0d34-0410-b5e6-96231b3b80d8
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lib/Target/X86
@ -4275,16 +4275,16 @@ def : Pat <(v8f64 (int_x86_avx512_rcp28_pd (v8f64 VR512:$src),
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multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr,
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SDNode OpNode, X86VectorVTInfo _>{
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defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
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defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
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(ins _.RC:$src), OpcodeStr, "$src", "$src",
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(_.FloatVT (OpNode _.RC:$src))>, EVEX;
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let mayLoad = 1 in {
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defm rm: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
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defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
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(ins _.MemOp:$src), OpcodeStr, "$src", "$src",
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(OpNode (_.FloatVT
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(bitconvert (_.LdFrag addr:$src))))>, EVEX;
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defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
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defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
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(ins _.ScalarMemOp:$src), OpcodeStr,
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"${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
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(OpNode (_.FloatVT
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@ -4388,10 +4388,10 @@ defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
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let Predicates = [HasAVX512] in {
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def : Pat<(v16f32 (int_x86_avx512_sqrt_ps_512 (v16f32 VR512:$src1),
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(bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_CURRENT)),
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(VSQRTPSZrr VR512:$src1)>;
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(VSQRTPSZr VR512:$src1)>;
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def : Pat<(v8f64 (int_x86_avx512_sqrt_pd_512 (v8f64 VR512:$src1),
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(bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_CURRENT)),
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(VSQRTPDZrr VR512:$src1)>;
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(VSQRTPDZr VR512:$src1)>;
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def : Pat<(f32 (fsqrt FR32X:$src)),
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(VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
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@ -5468,10 +5468,10 @@ bool X86InstrInfo::isHighLatencyDef(int opc) const {
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case X86::VSQRTSSm:
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case X86::VSQRTSSm_Int:
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case X86::VSQRTSSr:
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case X86::VSQRTPDZrm:
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case X86::VSQRTPDZrr:
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case X86::VSQRTPSZrm:
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case X86::VSQRTPSZrr:
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case X86::VSQRTPDZm:
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case X86::VSQRTPDZr:
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case X86::VSQRTPSZm:
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case X86::VSQRTPSZr:
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case X86::VSQRTSDZm:
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case X86::VSQRTSDZm_Int:
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case X86::VSQRTSDZr:
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