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Rework braindead conditionals I put in yesterday.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111974 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher 2010-08-24 22:07:27 +00:00
parent 9f782d4dcf
commit e24d66f525
1 changed files with 11 additions and 13 deletions
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24
lib/Target/ARM/ARMFastISel.cpp
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@ -365,20 +365,18 @@ bool ARMFastISel::ARMLoadAlloca(const Instruction *I) {
Value *Op0 = I->getOperand(0);
// Verify it's an alloca.
const Instruction *Inst = dyn_cast<Instruction>(Op0);
if (!Inst || Inst->getOpcode() != Instruction::Alloca) return false;
if (const AllocaInst *AI = dyn_cast<AllocaInst>(Op0)) {
DenseMap<const AllocaInst*, int>::iterator SI =
FuncInfo.StaticAllocaMap.find(AI);
const AllocaInst *AI = cast<AllocaInst>(Op0);
DenseMap<const AllocaInst*, int>::iterator SI =
FuncInfo.StaticAllocaMap.find(AI);
if (SI != FuncInfo.StaticAllocaMap.end()) {
unsigned ResultReg = createResultReg(FixedRC);
TII.loadRegFromStackSlot(*FuncInfo.MBB, *FuncInfo.InsertPt,
ResultReg, SI->second, FixedRC,
TM.getRegisterInfo());
UpdateValueMap(I, ResultReg);
return true;
if (SI != FuncInfo.StaticAllocaMap.end()) {
unsigned ResultReg = createResultReg(FixedRC);
TII.loadRegFromStackSlot(*FuncInfo.MBB, *FuncInfo.InsertPt,
ResultReg, SI->second, FixedRC,
TM.getRegisterInfo());
UpdateValueMap(I, ResultReg);
return true;
}
}
return false;