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R600/SI: Fold fabs/fneg into src input modifier

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208480 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Vincent Lejeune 2014-05-10 19:18:39 +00:00
parent 3378ca7d5c
commit e283f74133
3 changed files with 53 additions and 2 deletions
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33
lib/Target/R600/SIISelLowering.cpp
View File

@ -1323,6 +1323,7 @@ SDNode *SITargetLowering::foldOperands(MachineSDNode *Node,
// e64 version if available, -1 otherwise
int OpcodeE64 = AMDGPU::getVOPe64(Opcode);
const MCInstrDesc *DescE64 = OpcodeE64 == -1 ? nullptr : &TII->get(OpcodeE64);
int InputModifiers[3] = {0};
assert(!DescE64 || DescE64->getNumDefs() == NumDefs);
@ -1399,7 +1400,10 @@ SDNode *SITargetLowering::foldOperands(MachineSDNode *Node,
}
}
if (DescE64 && !Immediate) {
if (Immediate)
continue;
if (DescE64) {
// Test if it makes sense to switch to e64 encoding
unsigned OtherRegClass = DescE64->OpInfo[Op].RegClass;
@ -1418,6 +1422,31 @@ SDNode *SITargetLowering::foldOperands(MachineSDNode *Node,
DescE64 = nullptr;
}
}
if (!DescE64 && !Promote2e64)
continue;
if (!Operand.isMachineOpcode())
continue;
if (Operand.getMachineOpcode() == AMDGPU::FNEG_SI) {
Ops.pop_back();
Ops.push_back(Operand.getOperand(0));
InputModifiers[i] = 1;
Promote2e64 = true;
if (!DescE64)
continue;
Desc = DescE64;
DescE64 = 0;
}
else if (Operand.getMachineOpcode() == AMDGPU::FABS_SI) {
Ops.pop_back();
Ops.push_back(Operand.getOperand(0));
InputModifiers[i] = 2;
Promote2e64 = true;
if (!DescE64)
continue;
Desc = DescE64;
DescE64 = 0;
}
}
if (Promote2e64) {
@ -1425,7 +1454,7 @@ SDNode *SITargetLowering::foldOperands(MachineSDNode *Node,
Ops.clear();
for (unsigned i = 0; i < OldOps.size(); ++i) {
// src_modifier
Ops.push_back(DAG.getTargetConstant(0, MVT::i32));
Ops.push_back(DAG.getTargetConstant(InputModifiers[i], MVT::i32));
Ops.push_back(OldOps[i]);
}
// Add the modifier flags while promoting

11
test/CodeGen/R600/fabs.ll
View File

@ -49,6 +49,17 @@ entry:
ret void
}
; SI-CHECK-LABEL: @fabs_fold
; SI-CHECK-NOT: V_AND_B32_e32
; SI-CHECK: V_MUL_F32_e64 v{{[0-9]+}}, s{{[0-9]+}}, |v{{[0-9]+}}|
define void @fabs_fold(float addrspace(1)* %out, float %in0, float %in1) {
entry:
%0 = call float @fabs(float %in0)
%1 = fmul float %0, %in1
store float %1, float addrspace(1)* %out
ret void
}
declare float @fabs(float ) readnone
declare <2 x float> @llvm.fabs.v2f32(<2 x float> ) readnone
declare <4 x float> @llvm.fabs.v4f32(<4 x float> ) readnone

11
test/CodeGen/R600/fneg.ll
View File

@ -59,3 +59,14 @@ entry:
store float %1, float addrspace(1)* %out
ret void
}
; SI-CHECK-LABEL: @fneg_fold
; SI-CHECK-NOT: V_XOR_B32
; SI-CHECK: V_MUL_F32_e64 v{{[0-9]+}}, s{{[0-9]+}}, -v{{[0-9]+}}
define void @fneg_fold(float addrspace(1)* %out, float %in) {
entry:
%0 = fsub float -0.0, %in
%1 = fmul float %0, %in
store float %1, float addrspace(1)* %out
ret void
}