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Update DBG_VALUEs while breaking anti dependencies.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132487 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Devang Patel 2011-06-02 21:26:52 +00:00
parent 201cfcd6de
commit e29e8e100e
8 changed files with 42 additions and 29 deletions
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16
lib/CodeGen/AggressiveAntiDepBreaker.cpp
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@ -719,7 +719,9 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies(
const std::vector<SUnit>& SUnits,
MachineBasicBlock::iterator Begin,
MachineBasicBlock::iterator End,
unsigned InsertPosIndex) {
unsigned InsertPosIndex,
DbgValueVector &DbgValues) {
std::vector<unsigned> &KillIndices = State->GetKillIndices();
std::vector<unsigned> &DefIndices = State->GetDefIndices();
std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
@ -923,14 +925,10 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies(
// sure to update that as well.
const SUnit *SU = MISUnitMap[Q->second.Operand->getParent()];
if (!SU) continue;
for (unsigned i = 0, e = SU->DbgInstrList.size() ; i < e ; ++i) {
MachineInstr *DI = SU->DbgInstrList[i];
assert (DI->getNumOperands()==3 && DI->getOperand(0).isReg() &&
DI->getOperand(0).getReg()
&& "Non register dbg_value attached to SUnit!");
if (DI->getOperand(0).getReg() == AntiDepReg)
DI->getOperand(0).setReg(NewReg);
}
for (DbgValueVector::iterator DVI = DbgValues.begin(),
DVE = DbgValues.end(); DVI != DVE; ++DVI)
if (DVI->second == Q->second.Operand->getParent())
UpdateDbgValue(DVI->first, AntiDepReg, NewReg);
}
// We just went back in time and modified history; the

3
lib/CodeGen/AggressiveAntiDepBreaker.h
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@ -146,7 +146,8 @@ namespace llvm {
unsigned BreakAntiDependencies(const std::vector<SUnit>& SUnits,
MachineBasicBlock::iterator Begin,
MachineBasicBlock::iterator End,
unsigned InsertPosIndex);
unsigned InsertPosIndex,
DbgValueVector &DbgValues);
/// Observe - Update liveness information to account for the current
/// instruction, which will not be scheduled.

18
lib/CodeGen/AntiDepBreaker.h
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@ -30,6 +30,9 @@ namespace llvm {
/// anti-dependencies.
class AntiDepBreaker {
public:
typedef std::vector<std::pair<MachineInstr *, MachineInstr *> >
DbgValueVector;
virtual ~AntiDepBreaker();
/// Start - Initialize anti-dep breaking for a new basic block.
@ -40,9 +43,10 @@ public:
/// the number of anti-dependencies broken.
///
virtual unsigned BreakAntiDependencies(const std::vector<SUnit>& SUnits,
MachineBasicBlock::iterator Begin,
MachineBasicBlock::iterator End,
unsigned InsertPosIndex) =0;
MachineBasicBlock::iterator Begin,
MachineBasicBlock::iterator End,
unsigned InsertPosIndex,
DbgValueVector &DbgValues) = 0;
/// Observe - Update liveness information to account for the current
/// instruction, which will not be scheduled.
@ -52,6 +56,14 @@ public:
/// Finish - Finish anti-dep breaking for a basic block.
virtual void FinishBlock() =0;
/// UpdateDbgValue - Update DBG_VALUE if dependency breaker is updating
/// other machine instruction to use NewReg.
void UpdateDbgValue(MachineInstr *MI, unsigned OldReg, unsigned NewReg) {
assert (MI->isDebugValue() && "MI is not DBG_VALUE!");
if (MI && MI->getOperand(0).isReg() && MI->getOperand(0).getReg() == OldReg)
MI->getOperand(0).setReg(NewReg);
}
};
}

15
lib/CodeGen/CriticalAntiDepBreaker.cpp
View File

@ -421,7 +421,8 @@ unsigned CriticalAntiDepBreaker::
BreakAntiDependencies(const std::vector<SUnit>& SUnits,
MachineBasicBlock::iterator Begin,
MachineBasicBlock::iterator End,
unsigned InsertPosIndex) {
unsigned InsertPosIndex,
DbgValueVector &DbgValues) {
// The code below assumes that there is at least one instruction,
// so just duck out immediately if the block is empty.
if (SUnits.empty()) return 0;
@ -628,14 +629,10 @@ BreakAntiDependencies(const std::vector<SUnit>& SUnits,
// as well.
const SUnit *SU = MISUnitMap[Q->second->getParent()];
if (!SU) continue;
for (unsigned i = 0, e = SU->DbgInstrList.size() ; i < e ; ++i) {
MachineInstr *DI = SU->DbgInstrList[i];
assert (DI->getNumOperands()==3 && DI->getOperand(0).isReg() &&
DI->getOperand(0).getReg()
&& "Non register dbg_value attached to SUnit!");
if (DI->getOperand(0).getReg() == AntiDepReg)
DI->getOperand(0).setReg(NewReg);
}
for (DbgValueVector::iterator DVI = DbgValues.begin(),
DVE = DbgValues.end(); DVI != DVE; ++DVI)
if (DVI->second == Q->second->getParent())
UpdateDbgValue(DVI->first, AntiDepReg, NewReg);
}
// We just went back in time and modified history; the

3
lib/CodeGen/CriticalAntiDepBreaker.h
View File

@ -79,7 +79,8 @@ class TargetRegisterInfo;
unsigned BreakAntiDependencies(const std::vector<SUnit>& SUnits,
MachineBasicBlock::iterator Begin,
MachineBasicBlock::iterator End,
unsigned InsertPosIndex);
unsigned InsertPosIndex,
DbgValueVector &DbgValues);
/// Observe - Update liveness information to account for the current
/// instruction, which will not be scheduled.

2
lib/CodeGen/PostRASchedulerList.cpp
View File

@ -304,7 +304,7 @@ void SchedulePostRATDList::Schedule() {
if (AntiDepBreak != NULL) {
unsigned Broken =
AntiDepBreak->BreakAntiDependencies(SUnits, Begin, InsertPos,
InsertPosIndex);
InsertPosIndex, DbgValues);
if (Broken != 0) {
// We made changes. Update the dependency graph.

2
lib/CodeGen/ScheduleDAGInstrs.cpp
View File

@ -36,7 +36,7 @@ ScheduleDAGInstrs::ScheduleDAGInstrs(MachineFunction &mf,
: ScheduleDAG(mf), MLI(mli), MDT(mdt), MFI(mf.getFrameInfo()),
InstrItins(mf.getTarget().getInstrItineraryData()),
Defs(TRI->getNumRegs()), Uses(TRI->getNumRegs()),
FirstDbgValue(0), LoopRegs(MLI, MDT) {
LoopRegs(MLI, MDT), FirstDbgValue(0) {
DbgValues.clear();
}

12
lib/CodeGen/ScheduleDAGInstrs.h
View File

@ -110,10 +110,6 @@ namespace llvm {
std::vector<std::vector<SUnit *> > Defs;
std::vector<std::vector<SUnit *> > Uses;
/// DbgValues - Remember instruction that preceeds DBG_VALUE.
std::vector<std::pair<MachineInstr *, MachineInstr *> >DbgValues;
MachineInstr *FirstDbgValue;
/// PendingLoads - Remember where unknown loads are after the most recent
/// unknown store, as we iterate. As with Defs and Uses, this is here
/// to minimize construction/destruction.
@ -128,6 +124,14 @@ namespace llvm {
///
SmallSet<unsigned, 8> LoopLiveInRegs;
protected:
/// DbgValues - Remember instruction that preceeds DBG_VALUE.
typedef std::vector<std::pair<MachineInstr *, MachineInstr *> >
DbgValueVector;
DbgValueVector DbgValues;
MachineInstr *FirstDbgValue;
public:
MachineBasicBlock::iterator Begin; // The beginning of the range to
// be scheduled. The range extends