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Refactor some of the code that sets up the entry block for SjLj EH. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141323 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling
parent
bee5d2fac8
commit
e29fa1df55
@ -5483,8 +5483,11 @@ ARMTargetLowering::EmitAtomicBinary64(MachineInstr *MI, MachineBasicBlock *BB,
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return BB;
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}
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MachineBasicBlock *ARMTargetLowering::
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EmitSjLjDispatchBlock(MachineInstr *MI, MachineBasicBlock *MBB) const {
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/// SetupEntryBlockForSjLj - Insert code into the entry block that creates and
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/// registers the function context.
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void ARMTargetLowering::
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SetupEntryBlockForSjLj(MachineInstr *MI, MachineBasicBlock *MBB,
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MachineBasicBlock *DispatchBB, int FI) const {
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const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
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DebugLoc dl = MI->getDebugLoc();
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MachineFunction *MF = MBB->getParent();
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@ -5492,17 +5495,10 @@ EmitSjLjDispatchBlock(MachineInstr *MI, MachineBasicBlock *MBB) const {
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MachineConstantPool *MCP = MF->getConstantPool();
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ARMFunctionInfo *AFI = MF->getInfo<ARMFunctionInfo>();
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const Function *F = MF->getFunction();
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MachineFrameInfo *MFI = MF->getFrameInfo();
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int FI = MFI->getFunctionContextIndex();
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MachineBasicBlock *DispatchBB = MF->CreateMachineBasicBlock();
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// Shove the dispatch's address into the return slot in the function context.
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DispatchBB->setIsLandingPad();
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MBB->addSuccessor(DispatchBB);
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bool isThumb = Subtarget->isThumb();
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bool isThumb2 = Subtarget->isThumb2();
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unsigned PCLabelId = AFI->createPICLabelUId();
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unsigned PCAdj = (isThumb || isThumb2) ? 4 : 8;
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ARMConstantPoolValue *CPV =
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@ -5512,6 +5508,111 @@ EmitSjLjDispatchBlock(MachineInstr *MI, MachineBasicBlock *MBB) const {
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const TargetRegisterClass *TRC =
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isThumb ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass;
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// Grab constant pool and fixed stack memory operands.
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MachineMemOperand *CPMMO =
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MF->getMachineMemOperand(MachinePointerInfo::getConstantPool(),
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MachineMemOperand::MOLoad, 4, 4);
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MachineMemOperand *FIMMOSt =
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MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
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MachineMemOperand::MOStore, 4, 4);
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// Load the address of the dispatch MBB into the jump buffer.
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if (isThumb2) {
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// Incoming value: jbuf
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// ldr.n r5, LCPI1_1
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// orr r5, r5, #1
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// add r5, pc
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// str r5, [$jbuf, #+4] ; &jbuf[1]
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unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
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AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2LDRpci), NewVReg1)
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.addConstantPoolIndex(CPI)
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.addMemOperand(CPMMO));
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// Set the low bit because of thumb mode.
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unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
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AddDefaultCC(
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AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2ORRri), NewVReg2)
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.addReg(NewVReg1, RegState::Kill)
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.addImm(0x01)));
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unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
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BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg3)
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.addReg(NewVReg2, RegState::Kill)
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.addImm(PCLabelId);
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AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2STRi12))
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.addReg(NewVReg3, RegState::Kill)
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.addFrameIndex(FI)
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.addImm(36) // &jbuf[1] :: pc
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.addMemOperand(FIMMOSt));
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} else if (isThumb) {
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// Incoming value: jbuf
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// ldr.n r1, LCPI1_4
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// add r1, pc
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// mov r2, #1
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// orrs r1, r2
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// add r2, $jbuf, #+4 ; &jbuf[1]
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// str r1, [r2]
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unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
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AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tLDRpci), NewVReg1)
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.addConstantPoolIndex(CPI)
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.addMemOperand(CPMMO));
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unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
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BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg2)
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.addReg(NewVReg1, RegState::Kill)
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.addImm(PCLabelId);
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// Set the low bit because of thumb mode.
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unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
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AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tMOVi8), NewVReg3)
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.addReg(ARM::CPSR, RegState::Define)
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.addImm(1));
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unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
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AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tORR), NewVReg4)
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.addReg(ARM::CPSR, RegState::Define)
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.addReg(NewVReg2, RegState::Kill)
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.addReg(NewVReg3, RegState::Kill));
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unsigned NewVReg5 = MRI->createVirtualRegister(TRC);
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AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tADDrSPi), NewVReg5)
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.addFrameIndex(FI)
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.addImm(36)); // &jbuf[1] :: pc
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AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tSTRi))
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.addReg(NewVReg4, RegState::Kill)
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.addReg(NewVReg5, RegState::Kill)
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.addImm(0)
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.addMemOperand(FIMMOSt));
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} else {
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// Incoming value: jbuf
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// ldr r1, LCPI1_1
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// add r1, pc, r1
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// str r1, [$jbuf, #+4] ; &jbuf[1]
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unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
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AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::LDRi12), NewVReg1)
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.addConstantPoolIndex(CPI)
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.addImm(0)
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.addMemOperand(CPMMO));
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unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
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AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::PICADD), NewVReg2)
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.addReg(NewVReg1, RegState::Kill)
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.addImm(PCLabelId));
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AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::STRi12))
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.addReg(NewVReg2, RegState::Kill)
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.addFrameIndex(FI)
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.addImm(36) // &jbuf[1] :: pc
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.addMemOperand(FIMMOSt));
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}
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}
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MachineBasicBlock *ARMTargetLowering::
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EmitSjLjDispatchBlock(MachineInstr *MI, MachineBasicBlock *MBB) const {
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const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
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DebugLoc dl = MI->getDebugLoc();
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MachineFunction *MF = MBB->getParent();
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MachineRegisterInfo *MRI = &MF->getRegInfo();
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ARMFunctionInfo *AFI = MF->getInfo<ARMFunctionInfo>();
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MachineFrameInfo *MFI = MF->getFrameInfo();
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int FI = MFI->getFunctionContextIndex();
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const TargetRegisterClass *TRC =
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Subtarget->isThumb() ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass;
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// Get a mapping of the call site numbers to all of the landing pads they're
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// associated with.
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DenseMap<unsigned, SmallVector<MachineBasicBlock*, 2> > CallSiteNumToLPad;
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@ -5560,6 +5661,12 @@ EmitSjLjDispatchBlock(MachineInstr *MI, MachineBasicBlock *MBB) const {
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unsigned UId = AFI->createJumpTableUId();
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// Create the MBBs for the dispatch code.
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// Shove the dispatch's address into the return slot in the function context.
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MachineBasicBlock *DispatchBB = MF->CreateMachineBasicBlock();
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DispatchBB->setIsLandingPad();
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MBB->addSuccessor(DispatchBB);
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MachineBasicBlock *TrapBB = MF->CreateMachineBasicBlock();
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BuildMI(TrapBB, dl, TII->get(ARM::TRAP));
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DispatchBB->addSuccessor(TrapBB);
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@ -5574,105 +5681,20 @@ EmitSjLjDispatchBlock(MachineInstr *MI, MachineBasicBlock *MBB) const {
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MF->insert(MF->end(), TrapBB);
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MF->RenumberBlocks(Last);
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// Insert code into the entry block that creates and registers the function
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// context.
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SetupEntryBlockForSjLj(MI, MBB, DispatchBB, FI);
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// Grab constant pool and fixed stack memory operands.
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MachineMemOperand *CPMMO =
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MF->getMachineMemOperand(MachinePointerInfo::getConstantPool(),
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MachineMemOperand::MOLoad, 4, 4);
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MachineMemOperand *FIMMO =
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MachineMemOperand *FIMMOLd =
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MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
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MachineMemOperand::MOStore, 4, 4);
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// Load the address of the dispatch MBB into the jump buffer.
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if (isThumb2) {
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// Incoming value: jbuf
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// ldr.n r5, LCPI1_1
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// orr r5, r5, #1
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// add r5, pc
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// str r5, [$jbuf, #+4] ; &jbuf[1]
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unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
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AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2LDRpci), NewVReg1)
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.addConstantPoolIndex(CPI)
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.addMemOperand(CPMMO));
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// Set the low bit because of thumb mode.
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unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
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AddDefaultCC(
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AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2ORRri), NewVReg2)
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.addReg(NewVReg1, RegState::Kill)
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.addImm(0x01)));
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unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
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BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg3)
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.addReg(NewVReg2, RegState::Kill)
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.addImm(PCLabelId);
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AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2STRi12))
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.addReg(NewVReg3, RegState::Kill)
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.addFrameIndex(FI)
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.addImm(36) // &jbuf[1] :: pc
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.addMemOperand(FIMMO));
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} else if (isThumb) {
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// Incoming value: jbuf
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// ldr.n r1, LCPI1_4
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// add r1, pc
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// mov r2, #1
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// orrs r1, r2
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// add r2, $jbuf, #+4 ; &jbuf[1]
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// str r1, [r2]
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unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
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AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tLDRpci), NewVReg1)
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.addConstantPoolIndex(CPI)
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.addMemOperand(CPMMO));
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unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
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BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg2)
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.addReg(NewVReg1, RegState::Kill)
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.addImm(PCLabelId);
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// Set the low bit because of thumb mode.
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unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
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AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tMOVi8), NewVReg3)
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.addReg(ARM::CPSR, RegState::Define)
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.addImm(1));
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unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
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AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tORR), NewVReg4)
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.addReg(ARM::CPSR, RegState::Define)
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.addReg(NewVReg2, RegState::Kill)
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.addReg(NewVReg3, RegState::Kill));
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unsigned NewVReg5 = MRI->createVirtualRegister(TRC);
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AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tADDrSPi), NewVReg5)
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.addFrameIndex(FI)
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.addImm(36)); // &jbuf[1] :: pc
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AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tSTRi))
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.addReg(NewVReg4, RegState::Kill)
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.addReg(NewVReg5, RegState::Kill)
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.addImm(0)
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.addMemOperand(FIMMO));
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} else {
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// Incoming value: jbuf
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// ldr r1, LCPI1_1
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// add r1, pc, r1
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// str r1, [$jbuf, #+4] ; &jbuf[1]
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unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
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AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::LDRi12), NewVReg1)
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.addConstantPoolIndex(CPI)
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.addImm(0)
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.addMemOperand(CPMMO));
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unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
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AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::PICADD), NewVReg2)
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.addReg(NewVReg1, RegState::Kill)
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.addImm(PCLabelId));
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AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::STRi12))
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.addReg(NewVReg2, RegState::Kill)
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.addFrameIndex(FI)
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.addImm(36) // &jbuf[1] :: pc
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.addMemOperand(FIMMO));
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}
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FIMMO = MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
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MachineMemOperand::MOLoad, 4, 4);
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MachineMemOperand::MOLoad, 4, 4);
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unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
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AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2LDRi12), NewVReg1)
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.addFrameIndex(FI)
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.addImm(4)
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.addMemOperand(FIMMO));
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.addMemOperand(FIMMOLd));
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AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2CMPri))
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.addReg(NewVReg1)
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.addImm(LPadList.size()));
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@ -512,6 +512,10 @@ namespace llvm {
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bool signExtend,
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ARMCC::CondCodes Cond) const;
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void SetupEntryBlockForSjLj(MachineInstr *MI,
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MachineBasicBlock *MBB,
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MachineBasicBlock *DispatchBB, int FI) const;
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MachineBasicBlock *EmitSjLjDispatchBlock(MachineInstr *MI,
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MachineBasicBlock *MBB) const;
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