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ARM: R9 is not safe to use for tcGPR.

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Indirect tail-calls shouldn't use R9 for the branch destination, as
it's not reliably a call-clobbered register.

rdar://14793425

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188967 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2013-08-22 00:14:24 +00:00
parent 55d4c38074
commit e2a48fbd9d
2 changed files with 15 additions and 1 deletions
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2
lib/Target/ARM/ARMRegisterInfo.td
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@ -251,7 +251,7 @@ def hGPR : RegisterClass<"ARM", [i32], 32, (sub GPR, tGPR)>;
// to the saved value before the tail call, which would clobber a call address.
// Note, getMinimalPhysRegClass(R0) returns tGPR because of the names of
// this class and the preceding one(!) This is what we want.
def tcGPR : RegisterClass<"ARM", [i32], 32, (add R0, R1, R2, R3, R9, R12)> {
def tcGPR : RegisterClass<"ARM", [i32], 32, (add R0, R1, R2, R3, R12)> {
let AltOrders = [(and tcGPR, tGPR)];
let AltOrderSelect = [{
return MF.getTarget().getSubtarget<ARMSubtarget>().isThumb1Only();

14
test/CodeGen/Thumb2/tail-call-r9.ll Normal file
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@ -0,0 +1,14 @@
; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-m3 | FileCheck %s
@foo = common global void ()* null, align 4
; Make sure in the presence of a tail call, r9 doesn't get used to hold
; the destination address. It's callee-saved in AAPCS.
define arm_aapcscc void @test(i32 %a) nounwind {
; CHECK-LABEL: test:
; CHECK-NOT bx r9
%tmp = load void ()** @foo, align 4
tail call void asm sideeffect "", "~{r0},~{r1},~{r2},~{r3},~{r12}"() nounwind
tail call arm_aapcscc void %tmp() nounwind
ret void
}