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more tidying: name the components of PhysReg in the case when

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the target constraint specifies a specific physreg.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67618 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2009-03-24 15:27:37 +00:00
parent b3b4484e3d
commit e2f7bf8e2d
1 changed files with 9 additions and 8 deletions
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17
lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
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@ -4896,28 +4896,29 @@ GetRegistersForValue(SDISelAsmOperandInfo &OpInfo,
// If this is a constraint for a specific physical register, like {r17}, // If this is a constraint for a specific physical register, like {r17},
// assign it now. // assign it now.
if (PhysReg.first) { if (unsigned AssignedReg = PhysReg.first) {
const TargetRegisterClass *RC = PhysReg.second;
if (OpInfo.ConstraintVT == MVT::Other) if (OpInfo.ConstraintVT == MVT::Other)
ValueVT = *PhysReg.second->vt_begin(); ValueVT = *RC->vt_begin();
// Get the actual register value type. This is important, because the user // Get the actual register value type. This is important, because the user
// may have asked for (e.g.) the AX register in i32 type. We need to // may have asked for (e.g.) the AX register in i32 type. We need to
// remember that AX is actually i16 to get the right extension. // remember that AX is actually i16 to get the right extension.
RegVT = *PhysReg.second->vt_begin(); RegVT = *RC->vt_begin();
// This is a explicit reference to a physical register. // This is a explicit reference to a physical register.
Regs.push_back(PhysReg.first); Regs.push_back(AssignedReg);
// If this is an expanded reference, add the rest of the regs to Regs. // If this is an expanded reference, add the rest of the regs to Regs.
if (NumRegs != 1) { if (NumRegs != 1) {
TargetRegisterClass::iterator I = PhysReg.second->begin(); TargetRegisterClass::iterator I = RC->begin();
for (; *I != PhysReg.first; ++I) for (; *I != AssignedReg; ++I)
assert(I != PhysReg.second->end() && "Didn't find reg!"); assert(I != RC->end() && "Didn't find reg!");
// Already added the first reg. // Already added the first reg.
--NumRegs; ++I; --NumRegs; ++I;
for (; NumRegs; --NumRegs, ++I) { for (; NumRegs; --NumRegs, ++I) {
assert(I != PhysReg.second->end() && "Ran out of registers to allocate!"); assert(I != RC->end() && "Ran out of registers to allocate!");
Regs.push_back(*I); Regs.push_back(*I);
} }
} }