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CodeGen: Use MachineInstr& in IfConversion, NFC

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Switch to a range-based for in IfConverter::PredicateBlock and take
MachineInstr& in MaySpeculate to avoid an implicit conversion from
MachineBasicBlock::iterator to MachineInstr*.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274290 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Duncan P. N. Exon Smith 2016-06-30 23:04:51 +00:00
parent 8b7ef5c3e7
commit e4756450e1
1 changed files with 9 additions and 9 deletions
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18
lib/CodeGen/IfConversion.cpp
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@ -1588,14 +1588,14 @@ bool IfConverter::IfConvertDiamond(BBInfo &BBI, IfcvtKind Kind,
return true;
}
static bool MaySpeculate(const MachineInstr *MI,
static bool MaySpeculate(const MachineInstr &MI,
SmallSet<unsigned, 4> &LaterRedefs) {
bool SawStore = true;
if (!MI->isSafeToMove(nullptr, SawStore))
if (!MI.isSafeToMove(nullptr, SawStore))
return false;
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI.getOperand(i);
if (!MO.isReg())
continue;
unsigned Reg = MO.getReg();
@ -1616,8 +1616,8 @@ void IfConverter::PredicateBlock(BBInfo &BBI,
SmallSet<unsigned, 4> *LaterRedefs) {
bool AnyUnpred = false;
bool MaySpec = LaterRedefs != nullptr;
for (MachineBasicBlock::iterator I = BBI.BB->begin(); I != E; ++I) {
if (I->isDebugValue() || TII->isPredicated(*I))
for (MachineInstr &I : llvm::make_range(BBI.BB->begin(), E)) {
if (I.isDebugValue() || TII->isPredicated(I))
continue;
// It may be possible not to predicate an instruction if it's the 'true'
// side of a diamond and the 'false' side may re-define the instruction's
@ -1629,16 +1629,16 @@ void IfConverter::PredicateBlock(BBInfo &BBI,
// If any instruction is predicated, then every instruction after it must
// be predicated.
MaySpec = false;
if (!TII->PredicateInstruction(*I, Cond)) {
if (!TII->PredicateInstruction(I, Cond)) {
#ifndef NDEBUG
dbgs() << "Unable to predicate " << *I << "!\n";
dbgs() << "Unable to predicate " << I << "!\n";
#endif
llvm_unreachable(nullptr);
}
// If the predicated instruction now redefines a register as the result of
// if-conversion, add an implicit kill.
UpdatePredRedefs(*I, Redefs);
UpdatePredRedefs(I, Redefs);
}
BBI.Predicate.append(Cond.begin(), Cond.end());