From e4aafdf6a1848b52911f3fffbb9722ab1131477f Mon Sep 17 00:00:00 2001 From: Colin LeMahieu Date: Tue, 16 Dec 2014 17:44:49 +0000 Subject: [PATCH] [Hexagon] Adding absolute value, and negate with saturation git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224346 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Hexagon/HexagonInstrInfo.td | 34 ++++++++++++++++++---- test/MC/Disassembler/Hexagon/xtype_alu.txt | 10 +++++-- test/MC/Disassembler/Hexagon/xtype_bit.txt | 2 +- 3 files changed, 38 insertions(+), 8 deletions(-) diff --git a/lib/Target/Hexagon/HexagonInstrInfo.td b/lib/Target/Hexagon/HexagonInstrInfo.td index b5711c27fee..8a86ae98402 100644 --- a/lib/Target/Hexagon/HexagonInstrInfo.td +++ b/lib/Target/Hexagon/HexagonInstrInfo.td @@ -2688,6 +2688,11 @@ def NOT_rr64 : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1), "$dst = not($src1)", [(set (i64 DoubleRegs:$dst), (not (i64 DoubleRegs:$src1)))]>; + +//===----------------------------------------------------------------------===// +// STYPE/ALU - +//===----------------------------------------------------------------------===// + let hasSideEffects = 0 in class T_S2op_1 RegTyBits, RegisterClass RCOut, RegisterClass RCIn, bits<2> MajOp, bits<3> MinOp, bit isSat> @@ -2724,11 +2729,6 @@ def A2_sxtw : T_S2op_1_di <"sxtw", 0b01, 0b000>; def: Pat <(i64 (sext I32:$src)), (A2_sxtw I32:$src)>; -//===----------------------------------------------------------------------===// -// STYPE/ALU - -//===----------------------------------------------------------------------===// - - // Swizzle the bytes of a word let isCodeGenOnly = 0 in def A2_swiz : T_S2op_1_ii <"swiz", 0b10, 0b111>; @@ -2742,6 +2742,30 @@ let Defs = [USR_OVF], isCodeGenOnly = 0 in { def A2_satuh : T_S2op_1_ii <"satuh", 0b11, 0b101>; } +let Itinerary = S_2op_tc_2_SLOT23, isCodeGenOnly = 0 in { + // Absolute value word + def A2_abs : T_S2op_1_ii <"abs", 0b10, 0b100>; + + let Defs = [USR_OVF] in + def A2_abssat : T_S2op_1_ii <"abs", 0b10, 0b101, 1>; + + // Negate with saturation + let Defs = [USR_OVF] in + def A2_negsat : T_S2op_1_ii <"neg", 0b10, 0b110, 1>; +} + +def: Pat<(i32 (select (i1 (setlt (i32 IntRegs:$src), 0)), + (i32 (sub 0, (i32 IntRegs:$src))), + (i32 IntRegs:$src))), + (A2_abs IntRegs:$src)>; + +let AddedComplexity = 50 in +def: Pat<(i32 (xor (add (sra (i32 IntRegs:$src), (i32 31)), + (i32 IntRegs:$src)), + (sra (i32 IntRegs:$src), (i32 31)))), + (A2_abs IntRegs:$src)>; + + //===----------------------------------------------------------------------===// // STYPE/BIT + //===----------------------------------------------------------------------===// diff --git a/test/MC/Disassembler/Hexagon/xtype_alu.txt b/test/MC/Disassembler/Hexagon/xtype_alu.txt index 66bdc437901..4603432d173 100644 --- a/test/MC/Disassembler/Hexagon/xtype_alu.txt +++ b/test/MC/Disassembler/Hexagon/xtype_alu.txt @@ -1,5 +1,9 @@ # RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s +0x91 0xc0 0x95 0x8c +# CHECK: r17 = abs(r21) +0xb1 0xc0 0x95 0x8c +# CHECK: r17 = abs(r21):sat 0xf1 0xc2 0x15 0xe2 # CHECK: r17 += add(r21, #23) 0xf1 0xc2 0x95 0xe2 @@ -44,6 +48,8 @@ # CHECK: r17:16 = add(r21:20, r31:30):raw:hi 0x10 0xde 0xf4 0xd3 # CHECK: r17:16 = and(r21:20, r31:30) +0x50 0xde 0xf4 0xd3 +# CHECK: r17:16 = or(r21:20, r31:30) 0x71 0xdf 0x95 0xef # CHECK: r17 ^= xor(r21, r31) 0x11 0xdf 0xd5 0xd5 @@ -62,8 +68,8 @@ # CHECK: r17:16 = min(r21:20, r31:30) 0xf0 0xd4 0xbe 0xd3 # CHECK: r17:16 = minu(r21:20, r31:30) -0x50 0xde 0xf4 0xd3 -# CHECK: r17:16 = or(r21:20, r31:30) +0xd1 0xc0 0x95 0x8c +# CHECK: r17 = neg(r21):sat 0x71 0xd5 0x1f 0xef # CHECK: r17 += sub(r21, r31) 0x11 0xd5 0x3f 0xd5 diff --git a/test/MC/Disassembler/Hexagon/xtype_bit.txt b/test/MC/Disassembler/Hexagon/xtype_bit.txt index d0f63770d6b..021631dde55 100644 --- a/test/MC/Disassembler/Hexagon/xtype_bit.txt +++ b/test/MC/Disassembler/Hexagon/xtype_bit.txt @@ -1,4 +1,4 @@ # RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s 0x11 0xde 0x14 0xd0 -# CHECK: r17 = parity(r21:20, r31:30) \ No newline at end of file +# CHECK: r17 = parity(r21:20, r31:30)