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Better handling of OpcodeToISD using enum/switch.

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Patch by Pasi Parviainen <pasi.parviainen@iki.fi>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166773 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Renato Golin 2012-10-26 12:24:52 +00:00
parent 475832cc0f
commit e5372d6565
1 changed files with 67 additions and 66 deletions
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133
lib/Target/TargetTransformImpl.cpp
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@ -54,73 +54,74 @@ unsigned ScalarTargetTransformImpl::getJumpBufSize() const {
// Calls used by the vectorizers. // Calls used by the vectorizers.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
int InstructionOpcodeToISD(unsigned Opcode) { static int InstructionOpcodeToISD(unsigned Opcode) {
static const int OpToISDTbl[] = { enum InstructionOpcodes {
/*Instruction::Ret */ 0, // Opcode numbering start at #1. #define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM,
/*Instruction::Br */ 0, #define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM
/*Instruction::Switch */ 0, #include "llvm/Instruction.def"
/*Instruction::IndirectBr */ 0, };
/*Instruction::Invoke */ 0, switch (static_cast<InstructionOpcodes>(Opcode)) {
/*Instruction::Resume */ 0, case Ret: return 0;
/*Instruction::Unreachable */ 0, case Br: return 0;
/*Instruction::Add */ ISD::ADD, case Switch: return 0;
/*Instruction::FAdd */ ISD::FADD, case IndirectBr: return 0;
/*Instruction::Sub */ ISD::SUB, case Invoke: return 0;
/*Instruction::FSub */ ISD::FSUB, case Resume: return 0;
/*Instruction::Mul */ ISD::MUL, case Unreachable: return 0;
/*Instruction::FMul */ ISD::FMUL, case Add: return ISD::ADD;
/*Instruction::UDiv */ ISD::UDIV, case FAdd: return ISD::FADD;
/*Instruction::SDiv */ ISD::UDIV, case Sub: return ISD::SUB;
/*Instruction::FDiv */ ISD::FDIV, case FSub: return ISD::FSUB;
/*Instruction::URem */ ISD::UREM, case Mul: return ISD::MUL;
/*Instruction::SRem */ ISD::SREM, case FMul: return ISD::FMUL;
/*Instruction::FRem */ ISD::FREM, case UDiv: return ISD::UDIV;
/*Instruction::Shl */ ISD::SHL, case SDiv: return ISD::UDIV;
/*Instruction::LShr */ ISD::SRL, case FDiv: return ISD::FDIV;
/*Instruction::AShr */ ISD::SRA, case URem: return ISD::UREM;
/*Instruction::And */ ISD::AND, case SRem: return ISD::SREM;
/*Instruction::Or */ ISD::OR, case FRem: return ISD::FREM;
/*Instruction::Xor */ ISD::XOR, case Shl: return ISD::SHL;
/*Instruction::Alloca */ 0, case LShr: return ISD::SRL;
/*Instruction::Load */ ISD::LOAD, case AShr: return ISD::SRA;
/*Instruction::Store */ ISD::STORE, case And: return ISD::AND;
/*Instruction::GetElementPtr */ 0, case Or: return ISD::OR;
/*Instruction::Fence */ 0, case Xor: return ISD::XOR;
/*Instruction::AtomicCmpXchg */ 0, case Alloca: return 0;
/*Instruction::AtomicRMW */ 0, case Load: return ISD::LOAD;
/*Instruction::Trunc */ ISD::TRUNCATE, case Store: return ISD::STORE;
/*Instruction::ZExt */ ISD::ZERO_EXTEND, case GetElementPtr: return 0;
/*Instruction::SExt */ ISD::SEXTLOAD, case Fence: return 0;
/*Instruction::FPToUI */ ISD::FP_TO_UINT, case AtomicCmpXchg: return 0;
/*Instruction::FPToSI */ ISD::FP_TO_SINT, case AtomicRMW: return 0;
/*Instruction::UIToFP */ ISD::UINT_TO_FP, case Trunc: return ISD::TRUNCATE;
/*Instruction::SIToFP */ ISD::SINT_TO_FP, case ZExt: return ISD::ZERO_EXTEND;
/*Instruction::FPTrunc */ ISD::FP_ROUND, case SExt: return ISD::SEXTLOAD;
/*Instruction::FPExt */ ISD::FP_EXTEND, case FPToUI: return ISD::FP_TO_UINT;
/*Instruction::PtrToInt */ ISD::BITCAST, case FPToSI: return ISD::FP_TO_SINT;
/*Instruction::IntToPtr */ ISD::BITCAST, case UIToFP: return ISD::UINT_TO_FP;
/*Instruction::BitCast */ ISD::BITCAST, case SIToFP: return ISD::SINT_TO_FP;
/*Instruction::ICmp */ ISD::SETCC, case FPTrunc: return ISD::FP_ROUND;
/*Instruction::FCmp */ ISD::SETCC, case FPExt: return ISD::FP_EXTEND;
/*Instruction::PHI */ 0, case PtrToInt: return ISD::BITCAST;
/*Instruction::Call */ 0, case IntToPtr: return ISD::BITCAST;
/*Instruction::Select */ ISD::SELECT, case BitCast: return ISD::BITCAST;
/*Instruction::UserOp1 */ 0, case ICmp: return ISD::SETCC;
/*Instruction::UserOp2 */ 0, case FCmp: return ISD::SETCC;
/*Instruction::VAArg */ 0, case PHI: return 0;
/*Instruction::ExtractElement*/ ISD::EXTRACT_VECTOR_ELT, case Call: return 0;
/*Instruction::InsertElement */ ISD::INSERT_VECTOR_ELT, case Select: return ISD::SELECT;
/*Instruction::ShuffleVector */ ISD::VECTOR_SHUFFLE, case UserOp1: return 0;
/*Instruction::ExtractValue */ ISD::MERGE_VALUES, case UserOp2: return 0;
/*Instruction::InsertValue */ ISD::MERGE_VALUES, case VAArg: return 0;
/*Instruction::LandingPad */ 0}; case ExtractElement: return ISD::EXTRACT_VECTOR_ELT;
case InsertElement: return ISD::INSERT_VECTOR_ELT;
case ShuffleVector: return ISD::VECTOR_SHUFFLE;
case ExtractValue: return ISD::MERGE_VALUES;
case InsertValue: return ISD::MERGE_VALUES;
case LandingPad: return 0;
}
assert((Instruction::Ret == 1) && (Instruction::LandingPad == 58) && llvm_unreachable("Unknown instruction type encountered!");
"Instruction order had changed");
// Opcode numbering starts at #1 but the table starts at #0, so we subtract
// one from the opcode number.
return OpToISDTbl[Opcode - 1];
} }
std::pair<unsigned, EVT> std::pair<unsigned, EVT>