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R600/SI: Add support for work item and work group intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183138 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard
parent
e7397ee81a
commit
e5fcc0dee4
@ -33,8 +33,9 @@ protected:
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/// MachineFunction.
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///
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/// \returns a RegisterSDNode representing Reg.
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SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC,
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unsigned Reg, EVT VT) const;
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virtual SDValue CreateLiveInRegister(SelectionDAG &DAG,
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const TargetRegisterClass *RC,
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unsigned Reg, EVT VT) const;
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bool isHWTrueValue(SDValue Op) const;
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bool isHWFalseValue(SDValue Op) const;
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@ -76,6 +76,8 @@ SITargetLowering::SITargetLowering(TargetMachine &TM) :
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setOperationAction(ISD::SIGN_EXTEND, MVT::i64, Custom);
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setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
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setTargetDAGCombine(ISD::SELECT_CC);
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setTargetDAGCombine(ISD::SETCC);
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@ -83,6 +85,23 @@ SITargetLowering::SITargetLowering(TargetMachine &TM) :
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setSchedulingPreference(Sched::RegPressure);
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}
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SDValue SITargetLowering::LowerParameter(SelectionDAG &DAG, EVT VT,
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SDLoc DL, SDValue Chain,
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unsigned Offset) const {
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MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
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PointerType *PtrTy = PointerType::get(VT.getTypeForEVT(*DAG.getContext()),
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AMDGPUAS::CONSTANT_ADDRESS);
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EVT ArgVT = MVT::getIntegerVT(VT.getSizeInBits());
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SDValue BasePtr = DAG.getCopyFromReg(Chain, DL,
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MRI.getLiveInVirtReg(AMDGPU::SGPR0_SGPR1), MVT::i64);
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SDValue Ptr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
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DAG.getConstant(Offset, MVT::i64));
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return DAG.getExtLoad(ISD::ZEXTLOAD, DL, VT, Chain, Ptr,
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MachinePointerInfo(UndefValue::get(PtrTy)),
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VT, false, false, ArgVT.getSizeInBits() >> 3);
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}
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SDValue SITargetLowering::LowerFormalArguments(
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SDValue Chain,
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CallingConv::ID CallConv,
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@ -153,12 +172,11 @@ SDValue SITargetLowering::LowerFormalArguments(
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CCInfo.AllocateReg(AMDGPU::VGPR1);
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}
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unsigned ArgReg = 0;
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// The pointer to the list of arguments is stored in SGPR0, SGPR1
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if (Info->ShaderType == ShaderType::COMPUTE) {
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CCInfo.AllocateReg(AMDGPU::SGPR0);
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CCInfo.AllocateReg(AMDGPU::SGPR1);
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ArgReg = MF.addLiveIn(AMDGPU::SGPR0_SGPR1, &AMDGPU::SReg_64RegClass);
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MF.addLiveIn(AMDGPU::SGPR0_SGPR1, &AMDGPU::SReg_64RegClass);
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}
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AnalyzeFormalArguments(CCInfo, Splits);
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@ -175,17 +193,10 @@ SDValue SITargetLowering::LowerFormalArguments(
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EVT VT = VA.getLocVT();
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if (VA.isMemLoc()) {
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assert(ArgReg);
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PointerType *PtrTy = PointerType::get(VT.getTypeForEVT(*DAG.getContext()),
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AMDGPUAS::CONSTANT_ADDRESS);
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EVT ArgVT = MVT::getIntegerVT(VT.getSizeInBits());
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SDValue BasePtr = DAG.getCopyFromReg(DAG.getRoot(), DL,
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ArgReg, MVT::i64);
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SDValue Ptr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
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DAG.getConstant(VA.getLocMemOffset(), MVT::i64));
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SDValue Arg = DAG.getExtLoad(ISD::ZEXTLOAD, DL, VT, DAG.getRoot(), Ptr,
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MachinePointerInfo(UndefValue::get(PtrTy)),
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VA.getValVT(), false, false, ArgVT.getSizeInBits() >> 3);
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// The first 36 bytes of the input buffer contains information about
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// thread group and global sizes.
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SDValue Arg = LowerParameter(DAG, VT, DL, DAG.getRoot(),
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36 + VA.getLocMemOffset());
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InVals.push_back(Arg);
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continue;
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}
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@ -293,6 +304,54 @@ SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
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case ISD::BRCOND: return LowerBRCOND(Op, DAG);
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case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
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case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, DAG);
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case ISD::INTRINSIC_WO_CHAIN: {
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unsigned IntrinsicID =
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cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
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EVT VT = Op.getValueType();
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SDLoc DL(Op);
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//XXX: Hardcoded we only use two to store the pointer to the parameters.
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unsigned NumUserSGPRs = 2;
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switch (IntrinsicID) {
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default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
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case Intrinsic::r600_read_ngroups_x:
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return LowerParameter(DAG, VT, DL, DAG.getEntryNode(), 0);
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case Intrinsic::r600_read_ngroups_y:
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return LowerParameter(DAG, VT, DL, DAG.getEntryNode(), 4);
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case Intrinsic::r600_read_ngroups_z:
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return LowerParameter(DAG, VT, DL, DAG.getEntryNode(), 8);
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case Intrinsic::r600_read_global_size_x:
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return LowerParameter(DAG, VT, DL, DAG.getEntryNode(), 12);
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case Intrinsic::r600_read_global_size_y:
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return LowerParameter(DAG, VT, DL, DAG.getEntryNode(), 16);
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case Intrinsic::r600_read_global_size_z:
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return LowerParameter(DAG, VT, DL, DAG.getEntryNode(), 20);
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case Intrinsic::r600_read_local_size_x:
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return LowerParameter(DAG, VT, DL, DAG.getEntryNode(), 24);
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case Intrinsic::r600_read_local_size_y:
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return LowerParameter(DAG, VT, DL, DAG.getEntryNode(), 28);
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case Intrinsic::r600_read_local_size_z:
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return LowerParameter(DAG, VT, DL, DAG.getEntryNode(), 32);
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case Intrinsic::r600_read_tgid_x:
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return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
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AMDGPU::SReg_32RegClass.getRegister(NumUserSGPRs + 0), VT);
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case Intrinsic::r600_read_tgid_y:
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return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
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AMDGPU::SReg_32RegClass.getRegister(NumUserSGPRs + 1), VT);
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case Intrinsic::r600_read_tgid_z:
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return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
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AMDGPU::SReg_32RegClass.getRegister(NumUserSGPRs + 2), VT);
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case Intrinsic::r600_read_tidig_x:
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return CreateLiveInRegister(DAG, &AMDGPU::VReg_32RegClass,
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AMDGPU::VGPR0, VT);
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case Intrinsic::r600_read_tidig_y:
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return CreateLiveInRegister(DAG, &AMDGPU::VReg_32RegClass,
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AMDGPU::VGPR1, VT);
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case Intrinsic::r600_read_tidig_z:
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return CreateLiveInRegister(DAG, &AMDGPU::VReg_32RegClass,
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AMDGPU::VGPR2, VT);
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}
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}
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}
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return SDValue();
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}
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@ -933,3 +992,12 @@ MachineSDNode *SITargetLowering::AdjustRegClass(MachineSDNode *N,
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}
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}
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}
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SDValue SITargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
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const TargetRegisterClass *RC,
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unsigned Reg, EVT VT) const {
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SDValue VReg = AMDGPUTargetLowering::CreateLiveInRegister(DAG, RC, Reg, VT);
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return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(DAG.getEntryNode()),
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cast<RegisterSDNode>(VReg)->getReg(), VT);
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}
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@ -24,6 +24,8 @@ class SITargetLowering : public AMDGPUTargetLowering {
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const SIInstrInfo * TII;
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const TargetRegisterInfo * TRI;
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SDValue LowerParameter(SelectionDAG &DAG, EVT VT, SDLoc DL,
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SDValue Chain, unsigned Offset) const;
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SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
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@ -59,6 +61,8 @@ public:
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SDNode *Node) const;
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int32_t analyzeImmediate(const SDNode *N) const;
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SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC,
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unsigned Reg, EVT VT) const;
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};
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} // End namespace llvm
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211
test/CodeGen/R600/work-item-intrinsics.ll
Normal file
211
test/CodeGen/R600/work-item-intrinsics.ll
Normal file
@ -0,0 +1,211 @@
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; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=R600-CHECK %s
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; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck --check-prefix=SI-CHECK %s
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; R600-CHECK: @ngroups_x
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; R600-CHECK: RAT_WRITE_CACHELESS_32_eg [[VAL:T[0-9]+\.X]]
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; R600-CHECK: VTX_READ_32 [[VAL]], [[VAL]], 0
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; SI-CHECK: @ngroups_x
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; SI-CHECK: S_LOAD_DWORD [[VAL:SGPR[0-9]+]], SGPR0_SGPR1, 0
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; SI-CHECK: V_MOV_B32_e32 [[VVAL:VGPR[0-9]+]], [[VAL]]
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; SI-CHECK: BUFFER_STORE_DWORD [[VVAL]]
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define void @ngroups_x (i32 addrspace(1)* %out) {
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entry:
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%0 = call i32 @llvm.r600.read.ngroups.x() #0
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store i32 %0, i32 addrspace(1)* %out
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ret void
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}
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; R600-CHECK: @ngroups_y
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; R600-CHECK: RAT_WRITE_CACHELESS_32_eg [[VAL:T[0-9]+\.X]]
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; R600-CHECK: VTX_READ_32 [[VAL]], [[VAL]], 4
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; SI-CHECK: @ngroups_y
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; SI-CHECK: S_LOAD_DWORD [[VAL:SGPR[0-9]+]], SGPR0_SGPR1, 1
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; SI-CHECK: V_MOV_B32_e32 [[VVAL:VGPR[0-9]+]], [[VAL]]
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; SI-CHECK: BUFFER_STORE_DWORD [[VVAL]]
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define void @ngroups_y (i32 addrspace(1)* %out) {
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entry:
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%0 = call i32 @llvm.r600.read.ngroups.y() #0
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store i32 %0, i32 addrspace(1)* %out
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ret void
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}
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; R600-CHECK: @ngroups_z
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; R600-CHECK: RAT_WRITE_CACHELESS_32_eg [[VAL:T[0-9]+\.X]]
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; R600-CHECK: VTX_READ_32 [[VAL]], [[VAL]], 8
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; SI-CHECK: @ngroups_z
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; SI-CHECK: S_LOAD_DWORD [[VAL:SGPR[0-9]+]], SGPR0_SGPR1, 2
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; SI-CHECK: V_MOV_B32_e32 [[VVAL:VGPR[0-9]+]], [[VAL]]
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; SI-CHECK: BUFFER_STORE_DWORD [[VVAL]]
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define void @ngroups_z (i32 addrspace(1)* %out) {
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entry:
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%0 = call i32 @llvm.r600.read.ngroups.z() #0
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store i32 %0, i32 addrspace(1)* %out
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ret void
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}
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; R600-CHECK: @global_size_x
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; R600-CHECK: RAT_WRITE_CACHELESS_32_eg [[VAL:T[0-9]+\.X]]
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; R600-CHECK: VTX_READ_32 [[VAL]], [[VAL]], 12
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; SI-CHECK: @global_size_x
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; SI-CHECK: S_LOAD_DWORD [[VAL:SGPR[0-9]+]], SGPR0_SGPR1, 3
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; SI-CHECK: V_MOV_B32_e32 [[VVAL:VGPR[0-9]+]], [[VAL]]
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; SI-CHECK: BUFFER_STORE_DWORD [[VVAL]]
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define void @global_size_x (i32 addrspace(1)* %out) {
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entry:
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%0 = call i32 @llvm.r600.read.global.size.x() #0
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store i32 %0, i32 addrspace(1)* %out
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ret void
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}
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; R600-CHECK: @global_size_y
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; R600-CHECK: RAT_WRITE_CACHELESS_32_eg [[VAL:T[0-9]+\.X]]
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; R600-CHECK: VTX_READ_32 [[VAL]], [[VAL]], 16
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; SI-CHECK: @global_size_y
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; SI-CHECK: S_LOAD_DWORD [[VAL:SGPR[0-9]+]], SGPR0_SGPR1, 4
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; SI-CHECK: V_MOV_B32_e32 [[VVAL:VGPR[0-9]+]], [[VAL]]
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; SI-CHECK: BUFFER_STORE_DWORD [[VVAL]]
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define void @global_size_y (i32 addrspace(1)* %out) {
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entry:
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%0 = call i32 @llvm.r600.read.global.size.y() #0
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store i32 %0, i32 addrspace(1)* %out
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ret void
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}
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; R600-CHECK: @global_size_z
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; R600-CHECK: RAT_WRITE_CACHELESS_32_eg [[VAL:T[0-9]+\.X]]
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; R600-CHECK: VTX_READ_32 [[VAL]], [[VAL]], 20
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; SI-CHECK: @global_size_z
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; SI-CHECK: S_LOAD_DWORD [[VAL:SGPR[0-9]+]], SGPR0_SGPR1, 5
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; SI-CHECK: V_MOV_B32_e32 [[VVAL:VGPR[0-9]+]], [[VAL]]
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; SI-CHECK: BUFFER_STORE_DWORD [[VVAL]]
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define void @global_size_z (i32 addrspace(1)* %out) {
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entry:
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%0 = call i32 @llvm.r600.read.global.size.z() #0
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store i32 %0, i32 addrspace(1)* %out
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ret void
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}
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; R600-CHECK: @local_size_x
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; R600-CHECK: RAT_WRITE_CACHELESS_32_eg [[VAL:T[0-9]+\.X]]
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; R600-CHECK: VTX_READ_32 [[VAL]], [[VAL]], 24
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; SI-CHECK: @local_size_x
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; SI-CHECK: S_LOAD_DWORD [[VAL:SGPR[0-9]+]], SGPR0_SGPR1, 6
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; SI-CHECK: V_MOV_B32_e32 [[VVAL:VGPR[0-9]+]], [[VAL]]
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; SI-CHECK: BUFFER_STORE_DWORD [[VVAL]]
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define void @local_size_x (i32 addrspace(1)* %out) {
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entry:
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%0 = call i32 @llvm.r600.read.local.size.x() #0
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store i32 %0, i32 addrspace(1)* %out
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ret void
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}
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; R600-CHECK: @local_size_y
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; R600-CHECK: RAT_WRITE_CACHELESS_32_eg [[VAL:T[0-9]+\.X]]
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; R600-CHECK: VTX_READ_32 [[VAL]], [[VAL]], 28
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; SI-CHECK: @local_size_y
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; SI-CHECK: S_LOAD_DWORD [[VAL:SGPR[0-9]+]], SGPR0_SGPR1, 7
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; SI-CHECK: V_MOV_B32_e32 [[VVAL:VGPR[0-9]+]], [[VAL]]
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; SI-CHECK: BUFFER_STORE_DWORD [[VVAL]]
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define void @local_size_y (i32 addrspace(1)* %out) {
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entry:
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%0 = call i32 @llvm.r600.read.local.size.y() #0
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store i32 %0, i32 addrspace(1)* %out
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ret void
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}
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; R600-CHECK: @local_size_z
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; R600-CHECK: RAT_WRITE_CACHELESS_32_eg [[VAL:T[0-9]+\.X]]
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; R600-CHECK: VTX_READ_32 [[VAL]], [[VAL]], 32
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; SI-CHECK: @local_size_z
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; SI-CHECK: S_LOAD_DWORD [[VAL:SGPR[0-9]+]], SGPR0_SGPR1, 8
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; SI-CHECK: V_MOV_B32_e32 [[VVAL:VGPR[0-9]+]], [[VAL]]
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; SI-CHECK: BUFFER_STORE_DWORD [[VVAL]]
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define void @local_size_z (i32 addrspace(1)* %out) {
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entry:
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%0 = call i32 @llvm.r600.read.local.size.z() #0
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store i32 %0, i32 addrspace(1)* %out
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ret void
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}
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; The tgid values are stored in SGPRs offset by the number of user SGPRs.
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; Currently we always use exactly 2 user SGPRs for the pointer to the
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; kernel arguments, but this may change in the future.
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; SI-CHECK: @tgid_x
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; SI-CHECK: V_MOV_B32_e32 [[VVAL:VGPR[0-9]+]], SGPR2
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; SI-CHECK: BUFFER_STORE_DWORD [[VVAL]]
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define void @tgid_x (i32 addrspace(1)* %out) {
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entry:
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%0 = call i32 @llvm.r600.read.tgid.x() #0
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store i32 %0, i32 addrspace(1)* %out
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ret void
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}
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; SI-CHECK: @tgid_y
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; SI-CHECK: V_MOV_B32_e32 [[VVAL:VGPR[0-9]+]], SGPR3
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; SI-CHECK: BUFFER_STORE_DWORD [[VVAL]]
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define void @tgid_y (i32 addrspace(1)* %out) {
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entry:
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%0 = call i32 @llvm.r600.read.tgid.y() #0
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store i32 %0, i32 addrspace(1)* %out
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ret void
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}
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; SI-CHECK: @tgid_z
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; SI-CHECK: V_MOV_B32_e32 [[VVAL:VGPR[0-9]+]], SGPR4
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; SI-CHECK: BUFFER_STORE_DWORD [[VVAL]]
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define void @tgid_z (i32 addrspace(1)* %out) {
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entry:
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%0 = call i32 @llvm.r600.read.tgid.z() #0
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store i32 %0, i32 addrspace(1)* %out
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ret void
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}
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; SI-CHECK: @tidig_x
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; SI-CHECK: BUFFER_STORE_DWORD VGPR0
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define void @tidig_x (i32 addrspace(1)* %out) {
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entry:
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%0 = call i32 @llvm.r600.read.tidig.x() #0
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store i32 %0, i32 addrspace(1)* %out
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ret void
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}
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; SI-CHECK: @tidig_y
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; SI-CHECK: BUFFER_STORE_DWORD VGPR1
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define void @tidig_y (i32 addrspace(1)* %out) {
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entry:
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%0 = call i32 @llvm.r600.read.tidig.y() #0
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store i32 %0, i32 addrspace(1)* %out
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ret void
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}
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; SI-CHECK: @tidig_z
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; SI-CHECK: BUFFER_STORE_DWORD VGPR2
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define void @tidig_z (i32 addrspace(1)* %out) {
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entry:
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%0 = call i32 @llvm.r600.read.tidig.z() #0
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store i32 %0, i32 addrspace(1)* %out
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ret void
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}
|
||||
|
||||
declare i32 @llvm.r600.read.ngroups.x() #0
|
||||
declare i32 @llvm.r600.read.ngroups.y() #0
|
||||
declare i32 @llvm.r600.read.ngroups.z() #0
|
||||
|
||||
declare i32 @llvm.r600.read.global.size.x() #0
|
||||
declare i32 @llvm.r600.read.global.size.y() #0
|
||||
declare i32 @llvm.r600.read.global.size.z() #0
|
||||
|
||||
declare i32 @llvm.r600.read.local.size.x() #0
|
||||
declare i32 @llvm.r600.read.local.size.y() #0
|
||||
declare i32 @llvm.r600.read.local.size.z() #0
|
||||
|
||||
declare i32 @llvm.r600.read.tgid.x() #0
|
||||
declare i32 @llvm.r600.read.tgid.y() #0
|
||||
declare i32 @llvm.r600.read.tgid.z() #0
|
||||
|
||||
declare i32 @llvm.r600.read.tidig.x() #0
|
||||
declare i32 @llvm.r600.read.tidig.y() #0
|
||||
declare i32 @llvm.r600.read.tidig.z() #0
|
||||
|
||||
attributes #0 = { readnone }
|
||||
Loading…
Reference in New Issue
Block a user