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add back the optimization that Nate added for shl X, (zext_inreg y)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21273 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -943,8 +943,18 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
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case ISD::SHL:
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case ISD::SRL:
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case ISD::SRA:
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if (N2.getOpcode() == ISD::SIGN_EXTEND_INREG)
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if (N2.getOpcode() == ISD::SIGN_EXTEND_INREG &&
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cast<MVTSDNode>(N2)->getExtraValueType() != MVT::i1)
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return getNode(Opcode, VT, N1, N2.getOperand(0));
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else if (N2.getOpcode() == ISD::AND)
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if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(N2.getOperand(1))) {
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// If the and is only masking out bits that cannot effect the shift,
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// eliminate the and.
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unsigned NumBits = MVT::getSizeInBits(VT);
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if ((AndRHS->getValue() & (NumBits-1)) == NumBits-1)
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return getNode(Opcode, VT, N1, N2.getOperand(0));
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}
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break;
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}
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@ -1040,8 +1050,19 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
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case ISD::SRA_PARTS:
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case ISD::SRL_PARTS:
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case ISD::SHL_PARTS:
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if (N3.getOpcode() == ISD::SIGN_EXTEND_INREG)
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if (N3.getOpcode() == ISD::SIGN_EXTEND_INREG &&
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cast<MVTSDNode>(N3)->getExtraValueType() != MVT::i1)
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return getNode(Opcode, VT, N1, N2, N3.getOperand(0));
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else if (N3.getOpcode() == ISD::AND)
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if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(N3.getOperand(1))) {
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// If the and is only masking out bits that cannot effect the shift,
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// eliminate the and.
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unsigned NumBits = MVT::getSizeInBits(VT)*2;
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if ((AndRHS->getValue() & (NumBits-1)) == NumBits-1)
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return getNode(Opcode, VT, N1, N2, N3.getOperand(0));
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}
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break;
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}
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