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[AArch64] Handle extract_subvector(..., 0) in ISel.

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Summary:
Lowering this pattern early to an `EXTRACT_SUBREG` was making it impossible to match larger patterns in tblgen that use `extract_subvector(..., 0)` as part of the their input pattern.

It seems like there will exist somewhere a better way of specifying this pattern over all relevant register value types, but I didn't manage to find it.

Reviewers: t.p.northover, jmolloy

Subscribers: aemerson, llvm-commits, rengolin

Differential Revision: http://reviews.llvm.org/D14207

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@252464 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Charlie Turner 2015-11-09 12:45:11 +00:00
parent f60aec48e9
commit e6e427c6b3
2 changed files with 20 additions and 18 deletions
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23
lib/Target/AArch64/AArch64ISelLowering.cpp
View File

@ -6395,24 +6395,11 @@ SDValue AArch64TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
unsigned Val = Cst->getZExtValue();
unsigned Size = Op.getValueType().getSizeInBits();
if (Val == 0) {
switch (Size) {
case 8:
return DAG.getTargetExtractSubreg(AArch64::bsub, dl, Op.getValueType(),
Op.getOperand(0));
case 16:
return DAG.getTargetExtractSubreg(AArch64::hsub, dl, Op.getValueType(),
Op.getOperand(0));
case 32:
return DAG.getTargetExtractSubreg(AArch64::ssub, dl, Op.getValueType(),
Op.getOperand(0));
case 64:
return DAG.getTargetExtractSubreg(AArch64::dsub, dl, Op.getValueType(),
Op.getOperand(0));
default:
llvm_unreachable("Unexpected vector type in extract_subvector!");
}
}
// This will get lowered to an appropriate EXTRACT_SUBREG in ISel.
if (Val == 0)
return Op;
// If this is extracting the upper 64-bits of a 128-bit vector, we match
// that directly.
if (Size == 64 && Val * VT.getVectorElementType().getSizeInBits() == 64)

15
lib/Target/AArch64/AArch64InstrInfo.td
View File

@ -5788,6 +5788,21 @@ def : Pat<(v16i8 (bitconvert (v8f16 FPR128:$src))),
(v16i8 (REV16v16i8 FPR128:$src))>;
}
def : Pat<(v4i16 (extract_subvector V128:$Rn, (i64 0))),
(EXTRACT_SUBREG V128:$Rn, dsub)>;
def : Pat<(v8i8 (extract_subvector V128:$Rn, (i64 0))),
(EXTRACT_SUBREG V128:$Rn, dsub)>;
def : Pat<(v2f32 (extract_subvector V128:$Rn, (i64 0))),
(EXTRACT_SUBREG V128:$Rn, dsub)>;
def : Pat<(v4f16 (extract_subvector V128:$Rn, (i64 0))),
(EXTRACT_SUBREG V128:$Rn, dsub)>;
def : Pat<(v2i32 (extract_subvector V128:$Rn, (i64 0))),
(EXTRACT_SUBREG V128:$Rn, dsub)>;
def : Pat<(v1i64 (extract_subvector V128:$Rn, (i64 0))),
(EXTRACT_SUBREG V128:$Rn, dsub)>;
def : Pat<(v1f64 (extract_subvector V128:$Rn, (i64 0))),
(EXTRACT_SUBREG V128:$Rn, dsub)>;
def : Pat<(v8i8 (extract_subvector (v16i8 FPR128:$Rn), (i64 1))),
(EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
def : Pat<(v4i16 (extract_subvector (v8i16 FPR128:$Rn), (i64 1))),